LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 270

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Synchronous Serial Interface (SSI)
13.2.4.7
270
In this configuration, during idle periods:
If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is
signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled.
After a further one-half SSIClk period, both master and slave data are enabled onto their
respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition.
Data is then captured on the rising edges and propagated on the falling edges of the SSIClk
signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until
the final bit of the last word has been captured, and then returns to its idle state as described
above.
For continuous back-to-back transfers, the SSIFss pin is held Low between successive data
words and termination is the same as that of the single word transfer.
MICROWIRE Frame Format
Figure 13-10 shows the MICROWIRE frame format, again for a single frame. Figure 13-11 shows
the same format when back-to-back frames are transmitted.
Figure 13-10. MICROWIRE Frame Format (Single Frame)
MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead
of full-duplex, using a master-slave message passing technique. Each serial transmission begins
with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this
transmission, no incoming data is received by the SSI. After the message has been sent, the
off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control
message has been sent, responds with the required data. The returned data is 4 to 16 bits in
length, making the total frame length anywhere from 13 to 25 bits.
In this configuration, during idle periods:
SSIClk is forced High
SSIFss is forced High
The transmit data line SSITx is arbitrarily forced Low
When the SSI is configured as a master, it enables the SSIClk pad
When the SSI is configured as a slave, it disables the SSIClk pad
SSIClk is forced Low
SSIFss is forced High
The transmit data line SSITx is arbitrarily forced Low
SSIClk
SSIFss
SSIRx
SSITx
MSB
8-bit control
Preliminary
LSB
0
MSB
output data
4 to 16 bits
LSB
July 5, 2006