LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 96

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Internal Memory
96
Reset
Reset
Type
Type
Bit/Field
Flash Memory Protection Read Enable and Program Enable (FMPRE and FMPPE)
Offset 0x130 and 0x134
RO
RO
31
15
0
0
31:8
7:0
Register 1: Flash Memory Protection Read Enable (FMPRE), offset 0x130
Register 2: Flash Memory Protection Program Enable (FMPPE), offset 0x134
Note:
These registers store the read-only (FMPRE) and execute-only (FMPPE) protection bits for each
2 KB flash block. This register is loaded during the power-on reset sequence.
The factory settings for the FMPRE and FMPPE registers are a value of 1 for all implemented
banks. This implements a policy of open access and programmability. The register bits may be
changed by writing the specific register bit. However, this register is R/W0; the user can only
change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1).
The changes are not permanent until the register is committed (saved), at which point the bit
change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by
executing a power-on reset sequence.
For additional information, see “Flash Memory Protection” on page 92.
RO
RO
30
14
0
0
reserved
Block7-
Block0
Name
RO
RO
Offset is relative to System Control base address of 0x400FE000
29
13
0
0
RO
RO
28
12
0
0
reserved
R/W0
RO
RO
27
11
Type
0
0
RO
RO
RO
26
10
0
0
RO
RO
25
0
9
0
Preliminary
Reset
0
1
RO
RO
24
0
8
0
reserved
Block7
R/W0
RO
23
0
7
1
Description
Reserved bits return an indeterminate value, and
should never be changed.
Enable 2 KB flash blocks to be written or erased
(FMPPE register), or executed or read (FMPRE
register). The policies may be combined as shown
in Table 7-1 on page 93.
Block6
R/W0
RO
22
0
6
1
Block5
R/W0
RO
21
0
5
1
Block4
R/W0
RO
20
0
4
1
Block3
R/W0
RO
0
19
3
1
Block2
R/W0
RO
0
18
2
1
Block1
R/W0
RO
0
17
July 5, 2006
1
1
Block0
R/W0
RO
0
16
0
1