LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 222

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Analog-to-Digital Converter (ADC)
222
Reset
Reset
Type
Type
ADC Sample Sequence Control 2 (ADCSSCTL2)
Offset 0x084
TS3
R/W
RO
31
15
0
0
Register 19: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084
This register contains the configuration information for each sample for a sequence executed with
Sample Sequencer 2. When configuring a sample sequence, the END bit must be set at some
point, whether it be after the first sample, last sample, or any sample in between.
This register is 16-bits wide and contains information for four possible samples. This register’s bit
fields are as shown in the diagram below. Bit field definitions are the same as those in the
ADCSSCTL0 register (see page 215) but are for Sample Sequencer 2.
Register 20: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088
This register contains the conversion results for samples collected with Sample Sequencer 2.
Reads of this register return conversion result data in the order sample 0, sample 1, and so on,
until the FIFO is empty. If the FIFO is not properly handled by software, overflow and underflow
conditions are registered in the ADCOSTAT and ADCUSTAT registers.
Bit fields and definitions are the same as ADCSSFIFO0 (see page 217) but are for FIFO 2.
Register 21: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C
This register provides a window into the Sample Sequencer FIFO 2, providing full/empty status
information as well as the positions of the head and tail pointers. The reset value of 0x100
indicates an empty FIFO.
This register has the same bit fields and definitions as ADCSSFSTAT0 (see page 218) but is for
FIFO 2.
IE3
R/W
RO
30
14
0
0
END3
R/W
RO
29
13
0
0
D3
R/W
RO
28
12
0
0
TS2
R/W
RO
27
11
0
0
IE2
R/W
RO
26
10
0
0
END2
R/W
RO
25
0
9
0
Preliminary
D2
R/W
RO
24
0
8
0
reserved
TS1
R/W
RO
23
0
7
0
IE1
R/W
RO
22
0
6
0
END1
R/W
RO
21
0
5
0
D1
R/W
RO
20
0
4
0
TS0
R/W
RO
19
0
3
0
IE0
R/W
RO
18
0
2
0
END0
R/W
RO
17
July 5, 2006
0
1
0
D0
R/W
RO
16
0
0
0