LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 272

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Synchronous Serial Interface (SSI)
13.3
272
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements
Initialization and Configuration
To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register.
For each of the frame formats, the SSI is configured using the following steps:
1.
2.
3.
4.
5.
As an example, assume the SSI must be configured to operate with the following parameters:
Assuming the system clock is 20 MHz, the bit rate calculation would be:
FSSIClk = FSysClk / (CPSDVR * (1 + SCR)) ' 1x106 = 20x106 / (CPSDVR * (1 + SCR))
In this case, if CPSDVR=2, SCR must be 9.
The configuration sequence would be as follows:
1.
2.
3.
Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration
changes.
Select whether the SSI is a master or slave:
a.
b.
c.
Configure the clock prescale divisor by writing the SSICPSR register.
Write the SSICR0 register with the following configuration:
–
–
–
–
Enable the SSI by setting the SSE bit in the SSICR1 register.
Master operation
Freescale SPI mode (SPO=1, SPH=1)
1 Mbps bit rate
8 data bits
Ensure that the SSE bit in the SSICR1 register is disabled.
Write the SSICR1 register with a value of 0x00000000.
Write the SSICPSR register with a value of 0x00000002.
Serial clock rate (SCR)
Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO)
The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF)
The data size (DSS)
For master operations, set the SSICR1 register to 0x00000000.
For slave mode (output enabled), set the SSICR1 register to 0x00000004.
For slave mode (output disabled), set the SSICR1 register to 0x0000000C.
SSIClk
SSIFss
SSIRx
Preliminary
t
Hold
=t
t
Setup
SSIClk
=(2*t
SSIClk
)
First RX data to be
sampled by SSI slave
July 5, 2006