LM3S301 Luminary Micro, Inc, LM3S301 Datasheet - Page 208

• Manufacturer Part Number: LM3S301
• Description: Lm3s301 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Analog-to-Digital Converter (ADC)
208
Reset
Reset
Type
Type
Bit/Field
ADC Overflow Status (ADCOSTAT)
Offset 0x010
RO
RO
31
15
0
0
31:4
3
2
1
0
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010
This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow
condition has been handled by software, the condition can be cleared by writing a 1 to the
corresponding bit position.
RO
RO
30
14
0
0
reserved
Name
OV3
OV2
OV1
OV0
RO
RO
29
13
0
0
RO
RO
28
12
0
0
R/W1C
R/W1C
R/W1C
R/W1C
Type
RO
RO
RO
27
11
0
0
RO
RO
26
10
0
0
reserved
Reset
0
0
0
0
0
RO
RO
25
0
9
0
Preliminary
RO
RO
24
Description
Reserved bits return an indeterminate value, and should
never be changed.
This bit specifies that the FIFO for Sample Sequencer 3 has
hit an overflow condition where the FIFO is full and a write
was requested. When an overflow is detected, the most
recent write is dropped and this bit is set by hardware to
indicate the occurrence of dropped data. This bit is cleared by
writing a 1.
This bit specifies that the FIFO for Sample Sequencer 2 has
hit an overflow condition where the FIFO is full and a write
was requested. When an overflow is detected, the most
recent write is dropped and this bit is set by hardware to
indicate the occurrence of dropped data. This bit is cleared by
writing a 1.
This bit specifies that the FIFO for Sample Sequencer 1 has
hit an overflow condition where the FIFO is full and a write
was requested. When an overflow is detected, the most
recent write is dropped and this bit is set by hardware to
indicate the occurrence of dropped data. This bit is cleared by
writing a 1.
This bit specifies that the FIFO for Sample Sequencer 0 has
hit an overflow condition where the FIFO is full and a write
was requested. When an overflow is detected, the most
recent write is dropped and this bit is set by hardware to
indicate the occurrence of dropped data. This bit is cleared by
writing a 1.
0
8
0
reserved
RO
RO
23
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
RO
RO
20
0
4
0
R/W1C
OV3
RO
19
0
3
0
R/W1C
OV2
RO
18
0
2
0
R/W1C
OV1
RO
17
July 5, 2006
0
1
0
R/W1C
OV0
RO
16
0
0
0