dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 18

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1628D1G25
Objective data sheet
10.2.8 Frame assembly
The /A/ characters provided in the initial alignment sequence are used to align the data
streams. Bits SEL_ILA[1:0] of register ILA_CNTRL (see
symbol triggers the initial lane alignment: 00 = 1
/A/ symbol, 11 = 4
they start propagating the received data to the frame assembly module at the same point
in time (bits SEL_LOCK[2:0]; see
This module can compensate up to 15 character clock period misalignments between
the lanes.
If initial lane alignment is not supported, the manual alignment mode can be used (see
Table 72
After the initial ILA sequence, the lane alignment monitoring starts. If the received user
data contains a K28.3 /A/ symbol:
The DAC1628D1G25 supports the following LMF configuration as described in the
JESD204B standard (register LMF_CTRL; see
Table 7.
[1]
[2]
•
•
•
its position is compared to the value of the alignment monitor counter (bit
ILA_MON_LNx; see
if two successive K28.3 /A/ symbols have been received at a wrong position, a
realignment takes place
if the buffers are empty or overflow, this is indicated by the registers
ILA_BUF_ERR_LN0 to ILA_BUF_ERR_LN3 (see
S is the number of samples per frame.
HD is the High-Density bit as described in the JESD204B specification.
and
LMF configuration
L-M-F
1-2-4
2-2-2
4-2-2
4-2-1
Table
All information provided in this document is subject to legal disclaimers.
th
77).
/A/ symbol. When all receivers have received their first selected /A/,
Rev. 1.1 — 10 October 2011
Table
90)
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Table
75).
S
1
1
2
1
[1]
st
Table
/A/ symbol, 01 = 2
87):
Table
DAC1628D1G25
Table
91)
75) select which K28.3 /A/
nd
/A/ symbol, 10 = 3
© NXP B.V. 2011. All rights reserved.
HD
0
1
0
0
[2]
18 of 133
rd