dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 27

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1628D1G25
Objective data sheet
10.10.2 Full-scale current adjustment
10.12 Analog output
10.11 Digital offset adjustment
The DAC current can also be adjusted by applying an external reference voltage to the
non-inverting input pin GAPOUT and disabling the internal band gap reference voltage
(bit GAP_PON; see
The default full-scale current (I
DACs independently via the serial interface from 8.1 mA to 34 mA.
The settings applied to DAC_A_GAIN[9:0] (see
DAC A:
The DAC_B_GAIN[9:0] (see
When the DAC1628D1G25 analog output is DC connected to the next stage, the digital
offset correction (bits DAC_A_OFFSET[15:0] and DAC_B_OFFSET[15:0]; see
can be used to adjust the common-mode level at the output of each DAC. It adds an offset
at the end of the digital part, just before the DACs. Following table shows the range of
variation of the digital offset.
Table 15.
The device has two output channels, each producing two complementary current outputs,
which enable the reduction of even-order harmonics and noise. The pins are
IOUTAP/IOUTAN and IOUTBP/IOUTBN. Connect these pins using a load resistor R
the 3.3 V analog power supply (V
Figure 13
parallel combination of NMOS current sources and associated switches for each
segment.
I
I
DAC_A_OFFSET[15:0]
DAC_B_OFFSET[15:0]
(two’s complement)
1000 0000 0000 0000
1000 0000 0000 0001
...
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0001
...
0111 1111 1111 1110
0111 1111 1111 1111
O fs
O fs
 
 


A
A


shows the equivalent analog output circuit of one DAC. This circuit includes a
Digital offset adjustment
=
=
8100
8100
All information provided in this document is subject to legal disclaimers.
+
+
Table
DAC_A_GAIN[9:0]
DAC_B_GAIN[9:0]
Rev. 1.1 — 10 October 2011
18).
Table
O(fs)
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
DDA(3V3)
) is 20 mA but further adjustments can be made to both
21) define the full-scale current of DAC B:


).
25.3
25.3
Offset applied
32768
32767
...
1
0
+1
...
+32766
+32767
Table
21) define the full-scale current of
DAC1628D1G25
© NXP B.V. 2011. All rights reserved.
Table
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L
26)
to
(7)
(8)