dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 29

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1628D1G25
Objective data sheet
10.15.1 Basic output configuration
10.14 Phase correction
10.15 Output configuration
Table 16
DATAB
Table 16.
The IQ-modulator which follows the DACs can have a phase imbalance which results in
undesired sidebands. By adjusting the phase between the I and Q channels, the spur can
be reduced.
Without compensation the I and Q have a phase difference of  / 2 (90°). The registers
PH_CORR_CTRL0 and PH_CORR_CTRL1(see
75.7 to 104.3. The two registers define a signed value that ranges from 2048 to +2048.
the equation: PH_CORR[12:0] / 16384 gives the resulting phase compensation
(in radians).
Using a differentially coupled transformer output (see
distortion performance. In addition, it helps to match the impedance and provides
electrical isolation.
DATAA; DATAB
0
...
512
...
1023
Fig 14. 1 V (p-p) differential output with transformer
Equation 9
shows the output current as a function of the auxiliary DACs data DATAA and
Auxiliary DAC transfer function
All information provided in this document is subject to legal disclaimers.
AUX_A[9:2]/AUX_A[1:0];
AUX_B[9:0]/AUX_B[1:0]
(binary coding)
00 0000 0000
...
10 0000 0000
...
11 1111 1111
to
Rev. 1.1 — 10 October 2011
Equation
DAC1628D
IOUTAN/IOUTBN
IOUTAP/IOUTBP
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
12.
0 mA to 20 mA
0 mA to 20 mA
IOUTAP/IOUTAN
IOUTBP/IOUTBN
V
V
O(cm)
O(dif)
I
0
...
1.1
...
2.2
AUXAP
= 1 V
= 2.8 V
Table
; I
3.3 V
3.3 V
AUXBP
Figure
50 Ω
50 Ω
22) ensure a phase variation from
DAC1628D1G25
2:1
(mA)
aaa-000273
14) provides optimum
50 Ω
I
2.2
...
1.1
...
0
AUXAN
© NXP B.V. 2011. All rights reserved.
; I
AUXBN
(mA)
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