dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 82

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 96.
Table 97.
Default settings are shown highlighted.
Table 98.
Default settings are shown highlighted.
Table 99.
Default settings are shown highlighted.
Table 100. INTR_MISC_ENA register (address 0Fh) bit description
Default settings are shown highlighted.
DAC1628D1G25
Objective data sheet
Bit
3
2
1
0
Address
0Bh
0Ch
Bit
7 to 6
5 to 4
3 to 2
1 to 0
Bit
7
Bit
7
6
5
4
3
Symbol
DEC_KOUT_UNEXP_LN3
DEC_KOUT_UNEXP_LN2
DEC_KOUT_UNEXP_LN1
DEC_KOUT_UNEXP_LN0
Symbol
CS_STATE_LN3[1:0]
CS_STATE_LN2[1:0]
CS_STATE_LN1[1:0]
CS_STATE_LN0[1:0]
Symbol
RST_BUFF_ERR_FLAGS
Symbol
INTR_EN_CS_INIT_LN3
INTR_EN_CS_INIT_LN2
INTR_EN_CS_INIT_LN1
INTR_EN_CS_INIT_LN0
INTR_EN_BUF_ERR_LN3
KOUT_UNEXPECTED_FLAG register (address 0Ah) bit description
LOCK_CNT_MON registers (address 0Bh to 0Ch) bit description
CS_STATE_LNX register (address 0Dh) bit description
RST_BUF_ERR_FLAGS register (address 0Eh) bit description
Register
LOCK_CNT_MON_LN01 7 to 4
LOCK_CNT_MON_LN23 7 to 4
Bit
3 to 0
3 to 0
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Access
R
R
R
R
Access
R
R
R
R
Access
R/W
Access
R/W
R/W
R/W
R/W
R/W
Symbol
LOCK_CNT_
MON_LN1[3:0]
MON_LN0[3:0]
LOCK_CNT_
MON_LN3[3:0]
MON_LN2[3:0]
LOCK_CNT_
LOCK_CNT_
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Value
-
-
-
-
Value
-
-
-
-
Value
Value
0
1
0
1
0
1
0
1
0
1
0
Access Value
R
R
Description
unexpected /K/ symbols found in lane 3
unexpected /K/ symbols found in lane 2
unexpected /K/ symbols found in lane 1
unexpected /K/ symbols found in lane 0
Description
monitor cs_state fsm lane 3 (see
monitor cs_state fsm lane 2 (see
monitor cs_state fsm lane 1 (see
monitor cs_state fsm lane 0 (see
Description
Description
no action
intr_misc in case cs_state_ln3 = cs_init
no action
intr_misc in case cs_state_ln2 = cs_init
no action
intr_misc in case cs_state_ln1 = cs_init
no action
intr_misc in case cs_state_ln0 = cs_init
no action
generate interrupt if ILA_BUF_ERR_LN3 = 1
reset ILA_BUF_ERR_LNx flags
-
-
-
-
DAC1628D1G25
Description
lock_state monitor synchronization
word alignment lane 1
lock_state monitor synchronization
word alignment lane 0
lock_state monitor synchronization
word alignment lane 3
lock_state monitor synchronization
word alignment lane 2
© NXP B.V. 2011. All rights reserved.
Table
Table
Table
Table
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