dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 91
dac1628d1g25
Manufacturer Part Number
dac1628d1g25
Description
Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
Manufacturer
NXP Semiconductors
Datasheet
1.DAC1628D1G25.pdf
(133 pages)
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NXP Semiconductors
Table 111. Lane 0 configuration registers (address 00h to 0Dh) bit description
Default settings are shown highlighted.
DAC1628D1G25
Objective data sheet
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
10.17.6.2 Page x08 bit definition detailed description
Register
LN0_CFG_0
LN0_CFG_1
LN0_CFG_2
LN0_CFG_3
LN0_CFG_4
LN0_CFG_5
LN0_CFG_6
LN0_CFG_7
LN0_CFG_8
LN0_CFG_9
LN0_CFG_10
LN0_CFG_11
LN0_CFG_12
LN0_CFG_13
The tables in this section contain detailed descriptions of the page x08 registers.
Bit
7 to 0
7 to 4
3 to 0
4 to 0
6
5
4 to 0
7 to 0
4 to 0
7 to 0
7 to 6
4 to 0
7 to 5
4 to 0
7 to 5
4 to 0
7
4 to 0
7 to 0
7 to 0
7 to 0
Symbol
LN0_DID[7:0]
LN0_ADJCNT[3:0]
LN0_BID[3:0]
LN0_LID[4:0]
LN0_ADJDIR
LN0_PHADJ
LN0_L[4:0]
LN0_F[7:0]
LN0_K[4:0]
LN0_M[7:0]
LN0_CS[1:0]
LN0_N[4:0]
LN0_SUBCLASSV[2:0]
LN0_N’[4:0]
LN0_JESDV
LN0_S[4:0]
LN0_HD
LN0_CF[4:0]
LN0_RES1[7:0]
LN0_RES2[7:0]
LN0_FCHK[7:0]
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 October 2011
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
Access Value
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
-
-
-
-
00
01
10
-
-
000
001
-
-
-
-
-
-
DAC1628D1G25
Description
lane 0 device ID
lane 0 adjustable counter
lane 0 bank ID
lane 0 lane ID
lane 0 adjustable direction
lane 0 adjustable phase
number of lanes minus 1
number of octets per frame
minus 1
number of frames per
multi-frame minus 1
number of converters per device
minus 1
number of control bits
converter resolution minus 1
lane 0 JSED204B subclass
version
number of bits per sample minus
1
Lane 0 JESD204 version
converter per frame cycle minus
1
high density
number of control words per
frame cycle
lane 0 reserved field
lane 0 reserved field
lane 0 checksum
number of samples per
subclass 0
subclass 1
subclass 2
version A
version B
© NXP B.V. 2011. All rights reserved.
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