dac1628d1g25 NXP Semiconductors, dac1628d1g25 Datasheet - Page 20

• Manufacturer Part Number: dac1628d1g25
• Description: Dual 16-bit Dac Jesd204b Interface Up To 1.25 Gsps; X2, X4 And X8 Interpolating
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1628D1G25
Objective data sheet
Fig 7.
RESET_N
(optional)
SCS_N
SCLK
SDIO
SDO
R/W indicates the mode access.
The RESET_N signal is not linked to the SPI interface but enable the reset of the registers to the default values.
SPI protocol
10.3.2 SPI timing description
R/W
Table 8.
In
Table 9.
A[4:0] indicates which register is being addressed. If a multiple transfer occurs, this
address points to the first register to be accessed. The address is then internally
decreased after each following data phase.
The SPI interface can operate at a frequency of up to 15 MHz.
timing.
R/W
0
1
N1
Table
N0
9, N1 and N0 indicate the number of bytes transferred after the instruction byte.
Read or Write mode access description
Number of bytes transferred
A4
N1
0
0
1
1
All information provided in this document is subject to legal disclaimers.
A3
Rev. 1.1 — 10 October 2011
A2
A1
Dual 16-bit DAC: JESD204B interface; up to 1.25 Gsps
A0
D7
D7
N0
0
1
0
1
D6
D6
Description
Write mode operation
Read mode operation
D5
D5
DAC1628D1G25
D4
D4
Number of bytes transferred
D3
D3
Figure 8
D2
D2
© NXP B.V. 2011. All rights reserved.
D1
D1
shows the SPI
1
2
3
4
D0
D0
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