mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 219

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mc68hc908mr24

Manufacturer Part Number
mc68hc908mr24
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
MC68HC908MR24 — Rev. 4.1
Freescale Semiconductor
NOTE:
NOTE:
TOIE — TIMA Overflow Interrupt Enable Bit
TSTOP — TIMA Stop Bit
Do not set the TSTOP bit before entering wait mode if the TIMA is
required to exit wait mode. Also when the TSTOP bit is set and the timer
is configured for input capture operation, input captures are inhibited
until the TSTOP bit is cleared.
TRST — TIMA Reset Bit
Setting the TSTOP and TRST bits simultaneously stops the TIMA
counter at a value of $0000.
when TOF is set and then writing a logic 0 to TOF. If another TIMA
overflow occurs before the clearing sequence is complete, then
writing logic 0 to TOF has no effect. Therefore, a TOF interrupt
request cannot be lost due to inadvertent clearing of TOF. Reset
clears the TOF bit. Writing a logic 1 to TOF has no effect.
This read/write bit enables TIMA overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
This read/write bit stops the TIMA counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIMA
counter until software clears the TSTOP bit.
Setting this write-only bit resets the TIMA counter and the TIMA
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIMA counter is reset and always reads as logic 0. Reset clears
the TRST bit.
1 = TIMA counter has reached modulo value.
0 = TIMA counter has not reached modulo value.
1 = TIMA overflow interrupts enabled
0 = TIMA overflow interrupts disabled
1 = TIMA counter stopped
0 = TIMA counter active
1 = Prescaler and TIMA counter cleared
0 = No effect
Timer Interface A (TIMA)
Timer Interface A (TIMA)
Advance Information
219

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