mc68hc908mr24 Freescale Semiconductor, Inc, mc68hc908mr24 Datasheet - Page 94

• Manufacturer Part Number: mc68hc908mr24
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
7.3 SIM Bus Clock Control and Generation
7.3.1 Bus Timing
7.3.2 Clock Startup from POR or LVI Reset
Advance Information
94
OSC1
PLL
CGMVCLK
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, CGMOUT, as shown in
from either an external oscillator or from the on-chip phase-locked loop
(PLL) circuit. See
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See
When the power-on reset (POR) module or the low-voltage inhibit (LVI)
module generates a reset, the clocks to the CPU and peripherals are
inactive and held in an inactive phase until after the 4096 CGMXCLK
cycle POR timeout has completed. The RST pin is driven low by the SIM
during this entire period. The internal bus (IBUS) clocks start upon
completion of the timeout.
MONITOR MODE
SELECT
CIRCUIT
CLOCK
USER MODE
BCS
CGM
Figure 7-2. CGM Clock Signals
PTC2
System Integration Module (SIM)
Section 8. Clock Generator Module
Section 8. Clock Generator Module
A
B S*
*WHEN S = 1,
CGMOUT = B
CGMXCLK
CGMOUT
Figure
MC68HC908MR24
7-2. This clock can come
SIM COUNTER
2
Freescale Semiconductor
SIM
GENERATORS
(CGM).
BUS CLOCK
(CGM).
—
Rev. 4.1