mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 17

• Manufacturer Part Number: mpc8560vt667jb
• Description: Mpc8560 Powerquicc Iii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

4.4 Real Time Clock Timing
Table 10
5 RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8560.
Table 12
Freescale Semiconductor
Required assertion time of HRESET
Minimum assertion time for SRESET
PLL input setup time with stable SYSCLK before
HRESET negation
Input setup time for POR configs (other than PLL config)
with respect to negation of HRESET
Input hold time for POR configs (including PLL config)
with respect to negation of HRESET
Maximum valid-to-high impedance time for actively
driven POR configs with respect to negation of HRESET
Notes:
1.SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8560. See the MPC8560
PLL lock times
DLL lock times
Notes:
1.DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio
2. The CCB clock is determined by the SYSCLK × platform PLL ratio.
RTC clock high time
RTC clock low time
PowerQUICC III™ Integrated Communications Processor Preliminary Reference Manual for more details.
results in the minimum and an 8:1 ratio results in the maximum.
provides the real time clock (RTC) AC timing specifications for the MPC8560.
provides the PLL and DLL lock times.
Parameter/Condition
Table 7
Parameter/Condition
Parameter/Condition
provides the RESET initialization AC timing specifications for the MPC8560.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Table 11. RESET Initialization Timing Specifications
Table 10. RTC AC Timing Specifications
Table 12. PLL and DLL Lock Times
Symbol
t
t
RTCH
RTCL
t
t
CCB_CLK
CCB_CLK
7680
Min
Min
—
2 x
2 x
Min
100
512
100
—
4
2
Typical
—
—
122,880
Max
100
Max
—
—
—
—
—
5
Max
—
—
CCB Clocks
SYSCLKs
SYSCLKs
SYSCLKs
SYSCLKs
Unit
Unit
Unit
μs
μs
μs
ns
ns
RESET Initialization
Notes
—
—
Notes
Notes
1, 2
—
—
—
1
1
1
1
17