mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 21

• Manufacturer Part Number: mpc8560vt667jb
• Description: Mpc8560 Powerquicc Iii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

Figure 5
Freescale Semiconductor
At recommended operating conditions with GV
MDQS epilogue end
Notes:
1.The symbols used for timing specifications follow the pattern of t
2.All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3.Maximum possible clock skew between a clock MCK[n] and its relative inverse clock MCK[n], or between a clock MCK[n]
4.ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK and MDQ/MECC/MDM/MDQS.
5.Note that t
6.Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
7.All outputs are referenced to the rising edge of MSYNC_IN (S) at the pins of the MPC8560. Note that t
8.Guaranteed by design.
9.Guaranteed by characterization.
inputs and t
timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (OX or DX). For
example, t
state until outputs (O) are valid (V) or output valid time. Also, t
memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
and a relative clock MCK[m] or MSYNC_OUT. Skew measured between complementary signals at GV
(DD) from the rising edge of the MSYNC_IN clock (SH) until the MDQS signal is valid (MH). t
through control of the DQSS override bits in the TIMING_CFG_2 register. These controls allow the relationship between
the synchronous clock control timing and the source-synchronous DQS domain to be modified by the user. For best
turnaround times, these may need to be set to delay t
t
a description and understanding of the timing modifications enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8560.
symbol conventions described in note 1. For example, t
the MSYNC_IN clock (SH) for the duration of the MDQS signal precharge period (MP).
DDSHME
provides the AC test load for the DDR bus.
DDSHMH
accordingly. See the MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual for
Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode (continued)
DDKHOV
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
follows the symbol conventions described in note 1. For example, t
symbolizes DDR timing (DD) for the time t
Notes:
1.Data input threshold measurement point.
2.Data output measurement point.
Output
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Symbol
Table 17. DDR SDRAM Measurement Conditions
V
V
OUT
TH
DD
of 2.5 V ± 5%.
Figure 5. DDR AC Test Load
Z
0
= 50 Ω
Symbol
t
DDSHME
MV
0.5 × GV
REF
DDSHMH
DDR
1
DDSHMP
± 0.31 V
DD
MCK
(first two letters of functional block)(signal)(state) (reference)(state)
DDKLDX
an additional 0.25t
describes the DDR timing (DD) from the rising edge of
for outputs. Output hold time can be read as DDR
memory clock reference (K) goes from the high (H)
Min
1.5
symbolizes DDR timing (DD) for the time t
R
L
Unit
= 50 Ω
V
V
MCK
DDSHMH
. This will also affect t
Notes
GV
1
2
Max
4.0
DD
describes the DDR timing
/2
DDSHMH
DDSHMP
can be modified
DD
Unit
ns
/2.
DDSHMP
follows the
DDR SDRAM
Notes
MCK
7, 8
and
for
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