mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 45

• Manufacturer Part Number: mpc8560vt667jb
• Description: Mpc8560 Powerquicc Iii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

Figure 16
Figure 24
specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when
the falling edge is the active edge.
Freescale Semiconductor
FCC outputs—internal clock (NMSI) delay
FCC outputs—external clock (NMSI) delay
SCC/SPI outputs—internal clock (NMSI) delay
SCC outputs—external clock (NMSI) delay
SPI output—external clock (NMSI) delay
TDM outputs/SI delay
Notes:
1.Output specifications are measured from the 50% level of the rising edge of Serial Clock to the 50% level of the
2.The symbols used for timing specifications follow the pattern of t
signal. Timings are measured at the pin.
(reference)(state)
t
high state (H) until outputs (O) are invalid (X).
COL/CRS width high (FCC)
Notes:
1.Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of
2.The symbols used for timing specifications herein follow the pattern of t
3.PIO and TIMER inputs and outputs are asynchronous to SYSCLK or any other externally visible clock.
FIKHOX
provides the AC test load for the CPM.
through
Serial Clock. Timings are measured at the pin.
block)(signal)(state) (reference)(state)
outputs. For example, t
input signals (I) reaching the valid state (V) relative to the reference clock t
state or setup time. And t
signals (I) reach the invalid state (X) relative to the reference clock t
or hold time.
PIO/TIMER inputs are internally synchronized to the CPM internal clock. PIO/TIMER outputs should be
treated as asynchronous.
symbolizes the FCC inputs internal timing (FI) for the time t
Figure 29
for inputs and t
Output
Table 34. CPM Input AC Timing Specifications
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Characteristic
Table 35. CPM Output AC Timing Specifications
represent the AC timing from
Characteristic
FIIVKH
(first two letters of functional block)(reference)(state)(signal)(state)
TDIXKH
symbolizes the FCC inputs internal timing (FI) with respect to the time the
for inputs and t
Figure 23. CPM AC Test Load
symbolizes the TDM timing (TD) with respect to the time the input
Z
0
= 50 Ω
(first two letters of functional block)(reference)(state)(signal)(state)
(first two letters of functional block)(signal)(state)
Table 34
Symbol
t
t
t
t
t
t
NEKHOX
SEKHOX
TDKHOX
FEKHOX
NIKHOX
FIKHOX
FCC
R
L
memory clock reference (K) goes from the
= 50 Ω
Symbol
2
FCC
and
(first two letters of functional
t
1
FCCH
(continued)
(K) going to the high (H) state
Table
FCC
2
Min
0.5
2.5
OV
1
2
2
2
1
(K) going to the high (H)
for outputs. For example,
DD
35. Note that although the
Min
/2
1.5
3
Max
5.5
10
11
11
8
8
Unit
CLK
for
Unit
ns
ns
ns
ns
ns
ns
CPM
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