mpc8560vt667jb Freescale Semiconductor, Inc, mpc8560vt667jb Datasheet - Page 20

• Manufacturer Part Number: mpc8560vt667jb
• Description: Mpc8560 Powerquicc Iii Integrated Communications Processor
• Manufacturer: Freescale Semiconductor, Inc

DDR SDRAM
6.2.2 DDR SDRAM Output AC Timing Specifications
For chip selects MCS1 and MCS2, there will always be at least 200 DDR memory clocks coming out of
self-refresh after an HRESET before a precharge occurs. This will not necessarily be the case for chip
selects MCS0 and MCS3.
6.2.2.1
Table 16
DDR SDRAM interface with the DDR DLL enabled.
20
At recommended operating conditions with GV
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
On chip Clock Skew
MCK[n] duty cycle
ADDR/CMD output valid
ADDR/CMD output invalid
Write CMD to first MDQS capture edge
MDQ/MECC/MDM output setup with respect to
MDQS
MDQ/MECC/MDM output hold with respect to
MDQS
MDQS preamble start
and
DLL Enabled Mode
Table 17
Parameter
Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode
provide the output AC timing specifications and measurement conditions for the
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
DD
of 2.5 V ± 5%.
t
Symbol
t
MCKH
MCKSKEW
t
t
t
t
t
t
t
t
DDKHDS,
DDKHDX,
DDKHOV
DDSHMH
DDSHMP
DDKHOX
DDKLDS
DDKLDX
t
MCK
/t
MCK
1
0.75 × t
t
MCK
1100
1200
1100
1200
Min
900
900
45
—
—
MCK
6
1
+ 1.5
+ 1.5
0.75 × t
t
MCK
Max
150
10
55
—
—
—
MCK
3
+ 4.0
+ 4.0
Freescale Semiconductor
Unit
ns
ps
ns
ns
ns
ps
ps
ns
%
Notes
3, 8
4, 9
4, 9
6, 9
6, 9
7, 8
2
8
5