ppc8572elpxavnd Freescale Semiconductor, Inc, ppc8572elpxavnd Datasheet - Page 125

• Manufacturer Part Number: ppc8572elpxavnd
• Description: Mpc8572e Powerquicc Iii Integrated Communications Processors
• Manufacturer: Freescale Semiconductor, Inc

21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8572E.
21.1
This device includes seven PLLs, as follows:
21.2
21.2.1
Each of the PLLs listed above is provided with power through independent power supply pins
(AV
AV
voltages are derived directly from V
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in
AV
one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of the 1023 FC-PBGA footprint, without the inductance of vias.
Freescale Semiconductor
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1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
2. There are two core PLLs whose ratios are individually configurable. Each e500 core PLL
3. The DDR Complex PLL generates the clocking for the DDR Controllers
4. The local bus PLL generates the clock for the local bus.
5. There is a PLL for the SerDes1 module to be used for PCI Express and Serial Rapid IO Interfaces.
6. There is a PLL for the SerDes2 module to be used for SGMII Interface.
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_SRDS2 respectively). The AV
pins. By providing independent filters to each PLL the opportunity to cause noise injection from
_PLAT, AV
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in
generates the core clock as a slave to the platform clock. The frequency ratio between the e500
core clock and the platform clock is selected using the e500 PLL ratio configuration bits as
described in
System Clocking
Power Supply Design
PLL Power Supply Filtering
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
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Section 19.3, “e500 Core PLL Ratio.”
_CORE0, AV
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_CORE1, AV
through a low frequency filter scheme such as the following.
level should always be equivalent to V
Section 19.2, “CCB/SYSCLK PLL Ratio.”
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_DDR, AV
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_LBIU, AV
pin being supplied to minimize
Figure
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62, one to each of the
, and preferably these
_SRDS1 and
System Design Information
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