ppc8572elpxavnd Freescale Semiconductor, Inc, ppc8572elpxavnd Datasheet - Page 132

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ppc8572elpxavnd

Manufacturer Part Number
ppc8572elpxavnd
Description
Mpc8572e Powerquicc Iii Integrated Communications Processors
Manufacturer
Freescale Semiconductor, Inc
Datasheet
System Design Information
132
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved
5.This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing
6. Asserting SRESET causes a machine check interrupt to the e500 cores.
Notes:
signal integrity.
to position B.
to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed
COP Connector
Physical Pinout
to fully control the processor as shown here.
11
13
15
1
1
3
5
7
9
Board Sources
No pin
KEY
From Target
10
12
16
4
6
8
2
(if any)
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
14
13
11
10
12
16
SRESET
HRESET
15
4
6
5
8
9
1
3
7
2
3
COP_CHKSTP_OUT
COP_CHKSTP_IN
COP_VDD_SENSE
COP_TMS
COP_TDO
COP_TDI
COP_TCK
COP_SRESET
COP_TRST
COP_HRESET
NC
Figure 66. JTAG Interface Connection
NC
NC
4
B
2
5
A
10 Ω
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
10 kΩ
OV
DD
CKSTP_IN1
SRESET
HRESET
TRST
CKSTP_OUT0
CKSTP_IN0
TMS
TDO
TDI
TCK
CKSTP_OUT1
Freescale Semiconductor
1
1
6

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