ppc8572elpxavnd Freescale Semiconductor, Inc, ppc8572elpxavnd Datasheet - Page 79

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ppc8572elpxavnd

Manufacturer Part Number
ppc8572elpxavnd
Description
Mpc8572e Powerquicc Iii Integrated Communications Processors
Manufacturer
Freescale Semiconductor, Inc
Datasheet
clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular
clock driver chip.
Figure 51
It assumes the DC levels of the clock driver are compatible with MPC8572E SerDes reference clock
input’s DC requirement.
15.2.4
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100KHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15MHz is filtered by the PLL. The most problematic phase noise
Freescale Semiconductor
Single-Ended
CLK Driver Chip
Clock Driver
LVPECL CLK
Driver Chip
Clock Driver
Clock Driver
Figure 50. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
AC Requirements for SerDes Reference Clocks
CLK_Out
CLK_Out
CLK_Out
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Figure 51. Single-Ended Connection (Reference Only)
33 Ω
R1
R1
100 Ω differential PWB trace
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
R2
R2
50 Ω
100 Ω differential PWB trace
10nF
10nF
10nF
SD n _REF_CLK
SD n _REF_CLK
SD n _REF_CLK
SD n _REF_CLK
50 Ω
50 Ω
High-Speed Serial Interfaces (HSSI)
50 Ω
50 Ω
MPC8572E
MPC8572E
SerDes Refer.
CLK Receiver
SerDes Refer.
CLK Receiver
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