ppc8572elpxavnd Freescale Semiconductor, Inc, ppc8572elpxavnd Datasheet - Page 128

• Manufacturer Part Number: ppc8572elpxavnd
• Description: Mpc8572e Powerquicc Iii Integrated Communications Processors
• Manufacturer: Freescale Semiconductor, Inc

System Design Information
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in
state under normal operating conditions as most have asynchronous behavior and spurious assertion gives
unpredictable results.
The following pins must NOT be pulled down during power-on reset: DMA_DACK[0:1], EC5_MDC,
HRESET_REQ, TRIG_OUT/READY_P0/QUIESCE, MSRCID[2:4], MDVAL, and ASLEEP. The
TEST_SEL pin must be set to a proper state during POR configuration. For more details, refer to the pinlist
table of the individual device.
21.7
The MPC8572E drivers are characterized over process, voltage, and temperature. For all buses, the driver
is a push-pull single-ended driver type (open drain for I
To measure Z
or GND. Then, the value of each resistor is varied until the pad voltage is OV
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R
OV
other in value. Then, Z
128
DD
/2. R
Output Buffer DC Impedance
P
then becomes the resistance of the pull-up devices. R
0
for the single-ended drivers, an external resistor is connected from the chip pad to OV
Figure
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
0
66. Care must be taken to ensure that these pins are maintained at a valid deasserted
= (R
P
+ R
Figure 64. Driver Impedance Measurement
Data
N
)/2.
2
C).
Pad
P
R
R
is trimmed until the voltage at the pad equals
OV
OGND
N
P
DD
P
and R
SW2
SW1
N
are designed to be close to each
DD
/2 (see
Freescale Semiconductor
Figure
64). The
DD