ppc8572elpxavnd Freescale Semiconductor, Inc, ppc8572elpxavnd Datasheet - Page 26

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ppc8572elpxavnd

Manufacturer Part Number
ppc8572elpxavnd
Description
Mpc8572e Powerquicc Iii Integrated Communications Processors
Manufacturer
Freescale Semiconductor, Inc
Datasheet
DDR2 and DDR3 SDRAM Controller
Figure 6
6.2.3
This section describes the DC and AC differential electrical specifications for the DDR2 and DDR3
SDRAM controller interface of the MPC8572E.
Table 18
MCK/MCK when in DDR2 mode.
26
DC Input Signal Voltage
DC Differential Input Voltage
AC Differential Input Voltage
DC Differential Output Voltage
AC Differential Output Voltage
AC Differential Cross-point Voltage
Input Midpoint Voltage
GVDD
GND
provides the AC test load for the DDR2 and DDR3 Controller bus.
V
provides the differential specifications for the MPC8572E differential signals MDQS/MDQS and
MP
Parameter/Condition
DDR2 and DDR3 SDRAM Differential Timing Specifications
VID specifies the input differential voltage |VTR -VCP| required for
switching, where VTR is the true input signal (such as MCK or MDQS) and
VCP is the complementary input signal (such as MCK or MDQS).
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
V
V
TR
CP
Output
V
IN
Table 18. DDR2 SDRAM Differential Electrical Characteristics
Figure 6. DDR2 and DDR3 Controller bus AC Test Load
V
Z
0
ID
= 50 Ω
or V
Symbol
V
V
V
OD
V
V
OHAC
V
V
IDAC
IXAC
OH
MP
IN
ID
NOTE
JEDEC: 0.5
–0.3
Min
R
L
V
= 50 Ω
IX
or V
JEDEC: GV
OX
GV
GV
DD
Max
DD
+ 0.3
DD
/2
+ 0.6
Freescale Semiconductor
Unit
mV
mV
mV
mV
mV
V
V
Notes

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