ppc8572elpxavnd Freescale Semiconductor, Inc, ppc8572elpxavnd Datasheet - Page 58

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ppc8572elpxavnd

Manufacturer Part Number
ppc8572elpxavnd
Description
Mpc8572e Powerquicc Iii Integrated Communications Processors
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Local Bus Controller (eLBC)
Figure 30
Table 51
disabled.
At recommended operating conditions with BV
58
Local bus cycle time
Local bus duty cycle
Internal launch/capture clock to LCLK delay
Input setup to local bus clock (except
LGTA/LUPWAIT)
LGTA/LUPWAIT input setup to local bus clock
Input hold from local bus clock (except
LGTA/LUPWAIT)
LGTA/LUPWAIT input hold from local bus clock
LA[27:31]/LCS[0:7]/LWE[0:3]/
describes the general timing parameters of the local bus interface at BV
through
LFALE/LOE/LFRE/LFWP
Output (Address) Signal:
LFWE/LBCTL/LFCLE/
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
LAD[0:31]/LDP[0:3]
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Parameter
Figure 30. Local Bus Signals, Non-Special Signals Only (PLL Enabled)
Figure 35
Output Signals:
Input Signals:
Table 51. Local Bus General Timing Parameters—PLL Bypassed
Input Signal:
LGTA/LFRB
LSYNC_IN
LUPWAIT
LAD[0:31]
LALE
show the local bus signals.
DD
t
t
LBKHOV1
LBKHOV2
of 3.3 V ± 5%
t
LBKHOV3
t
LBKHOV4
Symbol
t
LBKH/
t
t
t
t
t
LBIVKH1
LBIXKH1
LBKHKT
LBIVKL2
LBIXKL2
t
LBK
t
t
t
t
t
t
LBK
LBKHOX1
LBKHOX2
LBKHOX2
LBIVKH1
LBIVKH2
1
t
t
t
LBKHOZ1
LBKHOZ2
LBKHOZ2
t
LBOTOT
Min
-1.3
-1.3
2.3
5.8
5.7
12
43
t
t
LBIXKH1
LBIXKH2
Max
4.0
57
DD
= 3.3 V DC with PLL
Freescale Semiconductor
Unit
ns
ns
ns
ns
ns
ns
%
Notes
4, 5
4, 5
4, 5
4, 5
2

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