saa6712e NXP Semiconductors, saa6712e Datasheet - Page 17

• Manufacturer Part Number: saa6712e
• Description: Xga Rgb To Tft Graphics Engine
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.6
This serial interface consists of only two signals, the serial
clock line (SCL) and the serial data line (SDA).
The maximum supported frequency on this bus is 1 MHz.
Spikes with a maximum pulse length of 50 ns are
suppressed by the internal input filter.
The SAA6712E operates as a slave and cannot initiate
any data transfer, so the clock line is always input. Via the
data line, data is transmitted and received, so this pin must
be input/output. The SCL and SDA lines are driven by
open-drain stages and pull-up resistors. When a logic 0 is
applied, the bus is set to ground level via the output
buffers. When a logic 1 is applied, the output buffer
switches to 3-state and the pull-up resistors pull the bus up
to +5 V.
Data transfer changes on SDA are allowed only when SCL
is LOW. Data is sampled on the positive edge of SCL.
In Idle state the output buffers are in 3-state, and the bus
is HIGH. A data transfer must be initiated by an I
master device. This is done by sending a START condition
when SDA changes from HIGH to LOW when SCL is HIGH
(see Fig.5). The device address of the SAA6712E must
then be sent with the desired I/O direction.
1999 Aug 25
handbook, full pagewidth
handbook, full pagewidth
XGA RGB to TFT graphics engine
SDA
I
SCL
2
SDA
C-bus interface
SCL
D1
START condition
D0
A6
ACK
A5
D7
A4
Fig.5 Start of a data transfer.
Fig.6 End of a data transfer.
D6
A3
2
C-bus
D5
A2
17
D4
If the SAA6712E reads its device address, it
acknowledges this by sending a single bit ACK to the
master. If write mode was selected, the master sends the
register address to be written and then the data bytes.
If read mode was selected, the SAA6712E sends the data
bytes starting from the last address accessed either by
write command or the next address at a read command.
All byte transfers are acknowledged from the receiving
device. The data transfer is aborted by sending a STOP
condition, when SDA changes from LOW to HIGH when
SCL is HIGH (see Fig.6).
If a new address has to be read or written, it is possible to
send a new START condition without a preceding STOP
condition. In this case the bus is still occupied by the
master, and it can initiate a new data transfer. This is
useful for read activities, where at first the register address
must be sent in write mode and after that a read command
will be sent to read data from this and following addresses.
If the data transfer was a read transfer and the master was
receiver, the master must not generate an acknowledge
before the STOP condition.
A1
D3
A0
D2
R/W
acknowledge/
not acknowledge
D1
ACK
D0
acknowledge
R7
Preliminary specification
A/A
STOP condition
R6
SAA6712E
MHB249
R5
MHB248