saa6712e NXP Semiconductors, saa6712e Datasheet - Page 30

• Manufacturer Part Number: saa6712e
• Description: Xga Rgb To Tft Graphics Engine
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1999 Aug 25
Input interface
G
Hsync polarity
Vsync polarity
Clamp pulse polarity
Gain correction pulse polarity
ADC sample sequence
Input interface activation
V
Vertical sample offset from Vsync
H
Horizontal sample offset from Hsync
V
Vertical sample window length
H
Horizontal sample window length
C
Start of clamp pulse after active edge of Hsync
C
End of clamp pulse after active edge of Hsync
G
Delay of start of GAINC pulse from first edge of Hsync
G
Delay of end of pulse GAINC from second edge of Hsync
ERTICAL SAMPLE OFFSET
ERTICAL SAMPLE LENGTH
ORIZONTAL SAMPLE OFFSET
ORIZONTAL SAMPLE LENGTH
LAMP PULSE START
LAMP PULSE END
XGA RGB to TFT graphics engine
ENERAL PROGRAMMING
AIN CORRECTION PULSE START DELAY
AIN CORRECTION PULSE END DELAY
Hsync is active LOW, line starts at rising edge of pin VHS
Hsync is active HIGH, line starts at falling edge of pin VHS
Vsync is active LOW, line starts at rising edge of pin VVS
Vsync is active HIGH, line starts at falling edge of pin VVS
Pulse is active LOW
Pulse is active HIGH
Pulse is active LOW
Pulse is active HIGH
ADC 0 is sampled first after Hsync (video input port A, B, C)
ADC 1 is sampled first after Hsync (video input port D, E, F)
No data sampling
Data sampling enabled
NAME
30
SUBADDRESS
35 and 36
37 and 38
39 and 40
41 and 42
33
43
44
45
46
R/W
W
W
W
W
W
W
W
W
W
Preliminary specification
D0
D1
D2
D3
D4
D6
D10 to D0
D11 to D0
D10 to D0
D11 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
logic 0
logic 1
logic 0
logic 1
logic 0
logic 1
logic 0
logic 1
logic 0
logic 1
logic 0
logic 1
SAA6712E
DATA