saa6712e NXP Semiconductors, saa6712e Datasheet - Page 40

• Manufacturer Part Number: saa6712e
• Description: Xga Rgb To Tft Graphics Engine
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.2
8.2.1
For normal operation the SAA6712E uses two clock
inputs; pin VCLK and pin CLK. VCLK is used as the
sample clock provided by the external ADCs or decoder.
The frequency and the sample edges of this clock depend
on the number of ADCs connected, or on the video dot
clock:
The clock from pin CLK is used as an internal reference,
and it is the source clock for the internal PLL. The memory
clock MCLKO and panel clock PCLK are derived from the
PLL (see Fig.8):
Where N = pre-divider ratio, M = post-divider ratio and
1999 Aug 25
MCLKO
PCLK
5 MHz
H
Horizontal end delay of vertical sync pulse at pin PVS
H
Start of horizontal sync pulse at pin PHS
H
End of horizontal sync pulse at pin PHS
D
Start of border region and horizontal data qualifier at pin PDE
D
End of border region and horizontal data qualifier at pin PDE
H
Start of horizontal active video region
V
Vertical sync pulse end at pin PVS
M
Maximum reachable line length for length controlling
ERTICAL SYNC PULSE END
1 ADC mode: maximum VCLK frequency is 150 MHz
2 ADC mode: maximum VCLK frequency is 75 MHz.
ORIZONTAL DELAY OF END OF VERTICAL SYNC
ORIZONTAL SYNC PULSE START
ORIZONTAL SYNC PULSE END
ATA QUALIFIER START
ATA QUALIFIER END
ORIZONTAL ACTIVE REGION START
XGA RGB to TFT graphics engine
AXIMUM HORIZONTAL LINE LENGTH
Clock management
=
C
CLK
---------- -
=
CLK
---------- -
N
LOCK GENERATION AND MULTIPLEXING
N
CLK
---------- -
N
8 MHz
32
----- -
M
16
NAME
40
It is possible to drive the memory clock output directly
without the internal PLL via pin MCLKI. To achieve this the
programming flag pll_mclk must be set to logic 0.
The same is possible for the panel output clock. Therefore
the system clock CLK is used directly. The system clock is
controlled by pll_pclk which must be set to logic 0.
SUBADDRESS
218 and 219
220 and 221
222 and 223
224 and 225
226 and 227
228 and 229
230 and 231
232 and 233
R/W
W
W
W
W
W
W
W
W
Preliminary specification
D10 to D0
D10 to D0
D10 to D0
D10 to D0
D10 to D0
D10 to D0
D10 to D0
D10 to D0
SAA6712E
DATA