saa6712e NXP Semiconductors, saa6712e Datasheet - Page 44

• Manufacturer Part Number: saa6712e
• Description: Xga Rgb To Tft Graphics Engine
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.3.3
The GAINC signal is the delayed horizontal sync pulse (VHS). It is delayed with respect to half the dot clock. The first
edge of VHS is delayed by gainc_on_delay and the second edge by gainc_off_delay (see Fig.11). The polarity is
programmed by gainc_pol.
8.4
The SAA6712E can be used to build up auto-scan systems
using an external microcontroller. Therefore information
about the input resolution and timing are provided
(see Tables 5 and 6). The flags pos_vsync and pos_hsync
show the polarity of the synchronization signals at VVS
and VHS. If they are set to logic 1 they are active HIGH,
and their active edge is the falling edge. If these flags are
set to logic 0, they are active LOW.
For detecting Video Electronic Standard Association
(VESA) Power-down modes or a not connected input, the
presence of the synchronization signals will be detected:
it can be read via no_vsync, and no_hsync. These flags
are active HIGH. The timing of the applied RGB video input
can be taken from v_lines reporting the number of lines of
a full frame. The horizontal timing can be calculated from
h_clocks. This register shows the length of a line in
numbers of reference clock periods. The reference clock is
equal to the panel clock PCLK in double pixel output mode
(48 bits in parallel), or it is half the panel clock PCLK in
single pixel output mode (24 bits in parallel).
If one of the above mentioned flags or counters changes
its value, it can be assumed that a new graphics mode has
been applied. In this case an interrupt at pin INT will be
generated. This port is active LOW.
1999 Aug 25
handbook, full pagewidth
XGA RGB to TFT graphics engine
Video mode and synchronization signal
detection
RGB data
G
CLAMP
GAINC
AIN CORRECTION PULSE GENERATION
VHS
gainc_on_delay
Fig.11 Gain adjustment and clamp pulse generation.
gainc_off_delay
clamp_on
clamp_off
44
The reset can be cleared by writing a logic 1 to intr_clear
at address 24.
For adjusting the RGB input interface to a new graphics
mode, the registers of the section RGB auto adjustment
are to be used. With this auto adjustment support it is
possible to measure the number of blanking pixels and
lines between the end of the synchronization pulses and
the active video. The horizontal and vertical back porch
blanking can be read out at black_pixels and black_lines.
The number of active pixels or lines will be reported from
non_black_pixels and non_black_lines. The first value
should be used for tuning the sample clocks PLL so that
this value corresponds to the number of pixels to be
sampled horizontally in this specific graphics mode.
To distinguish between blanking and active video
ref_colour is used. If the sample values of all three colour
components are below this value the pixel is treated as a
blanking pixel, otherwise it is treated as active video.
Additionally a reference pixel can be defined with ref_line
and ref_pixel. The R, G, and B components of this pixel are
sampled and available at ref_pixel_red, ref_pixel_green,
and ref_pixel_blue. They can be used for fine tuning the
external PLL in frequency and phase and for colour gain
adjustment.
Preliminary specification
SAA6712E
MHB254