saa6712e NXP Semiconductors, saa6712e Datasheet - Page 3

• Manufacturer Part Number: saa6712e
• Description: Xga Rgb To Tft Graphics Engine
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1
1.1
1.2
1.3
1999 Aug 25
Digital single (24-bit) or dual (48-bit) channel RGB input
Data input of sampled RGB data with a pixel frequency
of maximum 150 MHz
Free definable data acquisition offsets and vertical
window size in single pixel increments, horizontal
window size in double pixel increments
Programmable pulses for ADC clamping and ADC gain
correction
Detection of presence of sync signals, and of their
polarities
Support for auto-adjustment functions for sample clock
frequency, phase, vertical and horizontal sample offset,
as well as colour adjustment
Maximum supported resolution of 1280
Super Extended Graphics Adapter (SXGA)
Support for detection of the applied graphics mode
(auto-scan).
Colour correction Look-Up Table (LUT)
Phase correct up and downscaling of the RGB data
Fully programmable scaling ratios
Independent horizontal and vertical scaling engine
Free definable position of the scaled input picture inside
the output picture with programmable border colour.
Character based internal On Screen Display (OSD)
Programmable character matrix sizes of either
24
12
Programmable width and height of the OSD window,
built from maximum 1152 characters
8 different colours for foreground and background
inclusive transparent colours
Overlay port for external OSD controller.
XGA RGB to TFT graphics engine
FEATURES
RGB video input
Video processing
On screen display
24 pixels (42 characters available) or
16 pixels (128 characters available)
1024 dots
3
1.4
1.5
1.6
Single pixel/clock (24-bit) or double pixel/clock (48-bit)
digital RGB output
Generation of synchronization and validation signals for
the Thin Film Transistor (TFT) display
Frame rate control (temporal dithering) for displaying
true colour graphics on high colour displays
Free programmable timing for displays of several
manufacturers.
Support of both 1M
128k
Maximum memory clock frequency of 125 MHz
Scalable memory size built of either 2, 3 or 4 SDRAM,
or of 1 or 2 SGRAM devices
Special mode for operation without external memory.
Internal Phase-Locked Loop (PLL) for memory and
panel clock generation from the system clock
I
Boundary scan test circuit and Joint Test Action Group
(JTAG) test controller
Pin compatible to SAA6721E
Programming compatible to SAA6721E.
2
C-bus interface with 2 selectable addresses
Video output
Memory interface
Miscellaneous
32 SGRAM devices
16 SDRAM, 256k
Preliminary specification
SAA6712E
32 SGRAM or