saa6712e NXP Semiconductors, saa6712e Datasheet - Page 35

• Manufacturer Part Number: saa6712e
• Description: Xga Rgb To Tft Graphics Engine
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1999 Aug 25
OSD overlay port
G
OSD overlay port activation
Sync pulse generation
Clock edge for sampling
Clock gating
Horizontal sync polarity
Vertical sync polarity
Overlay port active pixel qualifier polarity
Overlay port clock polarity
O
Start of horizontal sync pulse with respect to left frame border
O
Length of horizontal sync pulse
O
Delay between start of horizontal sync and valid overlay data
O
Horizontal length of overlay region
O
Vertical offset of overlay region
O
Vertical length of overlay region
XGA RGB to TFT graphics engine
ENERAL CONFIGURATION
VERLAY HORIZONTAL SYNC START
VERLAY HORIZONTAL SYNC LENGTH
VERLAY HORIZONTAL SYNC LATENCY
VERLAY WINDOW HORIZONTAL LENGTH
VERLAY WINDOW VERTICAL OFFSET
VERLAY WINDOW VERTICAL LENGTH
Overlay information will not be inserted into data stream
Overlay information will be inserted into data stream
No sync pulses will be generated
Sync pulses will be generated
Data sampling at falling edge of clock at pin OVCLK
Data sampling at rising edge of clock at pin OVCLK
OVCLK always enabled
OVCLK enabled only during internal active video processing
Active LOW horizontal sync pulse at pin OVHS
Active HIGH horizontal sync pulse at pin OVHS
Active LOW vertical sync pulse at pin OVVS
Active HIGH vertical sync pulse at pin OVVS
Active LOW qualifier signal at pin OVACT
Active HIGH qualifier signal at pin OVACT
Sync pulse change with respect to falling edge at pin OVCLK
Sync pulse change with respect to rising edge at pin OVCLK
NAME
35
SUBADDRESS
100 and 101
102 and 103
105 and 106
107 and 108
109 and 110
104
99
R/W
W
W
W
W
W
W
W
Preliminary specification
D0
D1
D2
D3
D4
D5
D6
D7
D10 to D0
D10 to D0
D7 to D0
D10 to D0
D10 to D0
D10 to D0
logic 0
logic 1
logic 0
logic 1
logic 0
logic 1
logic 0
logic 1
logic 0
logic 1
logic 0
logic 1
logic 0
logic 1
logic 0
logic 1
SAA6712E
DATA