saa6712e NXP Semiconductors, saa6712e Datasheet - Page 45

• Manufacturer Part Number: saa6712e
• Description: Xga Rgb To Tft Graphics Engine
• Manufacturer: NXP Semiconductors

Philips Semiconductors
8.5
The SAA6712E features a 64 bits wide synchronous
DRAM interface. Both SDRAM and SGRAM devices can
be used. There is no difference in programming when
using SDRAM or SGRAM devices. The only thing that
must be considered is the amount of frame buffer memory,
which must be enough for the specific application.
If not the whole bandwidth of the 64 bits wide data bus is
needed, the data bus can be downsized to 48 or 32 bits.
This is done with the parameter data_width, see Table 9.
Table 9 Data bus width
Since the different timing parameters of various RAM
device types are different, all important timing values are
programmable and must be set-up according to the used
RAM types.
Table 10 Memory interface limitations
8.5.2
All SGRAM and SDRAM devices must be powered-up and initialized correctly. The SAA6712E memory interface is
implemented to fulfil the INTEL PC100 SDRAM specification.
Table 11 shows the required programming steps to initialize the memory correctly.
1999 Aug 25
CAS latency
t
t
t
t
t
SDRAM_burst_length
burst_seq_length
t
data_width[1 and 0]
RCD
RRD
RP
WR
RC
RSC
XGA RGB to TFT graphics engine
TIMING SYMBOL
Memory interface
I
NITIALIZATION OF EXTERNAL MEMORY
0
1
2
Column Address Strobe (CAS)
latency
activate to command delay; Row
Address Strobe (RAS) to CAS delay
RAS to RAS bank activity delay
RAS precharge time
write recovery time
RAS cycle time
Register Set Cycle (RSC) mode time internally defined; cannot be
PROGRAMMED BUS WIDTH
PARAMETER
(BITS)
32
48
64
45
To reach a high effective bandwidth all access to the
external memory is organized in bursts. The larger the
number of subsequent read or write accesses the higher
the effective bandwidth. An effective bandwidth of 91%
can be reached by doing 64 words burst accesses.
The RAM devices support a maximum internal burst
length of 8 words only, so 8 of these bursts must be run
subsequently. This can be programmed by setting up the
RAM with SDRAM_burst_length_code taken from the
specification data of the SDRAM or SGRAM. The memory
interface must be programmed to 64 words bursts by
programming the RAM burst length SDRAM_burst_length
to 8, and the number of these bursts in burst_seq_length
to 8. The internal structure of the SAA6712E is optimized
for 64 words bursts.
8.5.1
The timing parameters of the memory access can be
programmed to fulfil the timing restrictions of several
SDRAM or SGRAM devices. But there are some
limitations, as shown in Table 10.
t
t
must be supported by
SDRAM
must be an even number
changed
RRD
RRD
= t
M
t
CONDITIONS
RCD
RCD
EMORY INTERFACE LIMITATIONS
; proposal is
+ 1
Preliminary specification
(CLOCK PERIODS)
MINIMUM VALUE
SAA6712E
=8
2
2
3
3
1
3
2
2