tmp88cu74 TOSHIBA Semiconductor CORPORATION, tmp88cu74 Datasheet
tmp88cu74
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tmp88cu74 Summary of contents
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... SLEEP mode: CPU stops, and Peripherals operate using low-frequency clock. Release by interrupts. × Wide operating voltage: 2 32.8 kHz, 4 12.5 MHz/32.8 kHz × Emulation Pod: BM88CU74F0A 23 µ MHz (High-speed conversion mode), 59 µs at 12.5 MHz (Low-speed conversion mode) 88CU74-2 TMP88CU74 2007-10-19 2003-02-17 ...
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... P01 88CU74-3 TMP88CU74 VDD VAREF VASS P53 (AIN11) P52 (AIN10) P51 (AIN9) P50 (AIN8) P47 (AIN7) P46 (AIN6) P45 (AIN5) P44 (AIN4) P43 (AIN3) P42 (AIN2) P41 (AIN1) P40 (AIN0) P32 ( SCK ...
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... Time Base Timer/Counters Timer/Counters Timer TC1 TC2 TC3 Watchdog Timer P53 (AIN11) P17 P50 (AIN8) P10 (Analog inputs) I/O port 88CU74-4 TMP88CU74 Program Memory (ROM) Serial bus Interfaces 2 TC4 SIO1 I C bus P0 P3 P07 P32 to to P00 P30 2007-10-19 2003-02-17 ...
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... When used as an vacuum fluorescent tube driver output, the output latch must be cleared to “0”. VTF output 5-bit high breakdown voltage output ports with the latch. When used as an vacuum fluorescent tube driver output, the latch must be cleared to “0”. 88CU74-5 TMP88CU74 2007-10-19 2003-02-17 ...
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... Reset signal input or watchdog timer output/address-reset output/system clock reset output. TEST Input Test pin for out-going teset. Be tied to low. VDD, VSS + (GND) Power Supply VKK Vacuum fluore scent tube driver voltage pin. VAREF, VASS Analog reference voltage input (High, Low) Function 88CU74-6 TMP88CU74 2007-10-19 2003-02-17 ...
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... Memory Address Map TLCS-870/X Series, the memory is organized 4 address spaces (ROM, RAM, SFR, and DBR). Figure 1.1.1 shows the memory address maps of the TMP88CU74. It uses a memory mapped I/O system, and all I/O registers are mapped in the SFR/DBR address spaces. There are 16 banks of general-purpose registers. ...
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... Data Memory (RAM) The TMP88CU74 has 2 Kbytes of static RAM (address 00040H to 0083FH). The first 128 bytes (00040H to 000BFH) of the internal RAM are also used as general-purpose register banks. The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. ...
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... DVCR), and DV7CK(bit 4 in TBTCR), that is shown in Table 1.4.1. As reset and STOP mode started/canceled, The prescaler and the divider are cleared to “0”. Low-frequency clock XOUT XTIN XTOUT (Open) (c) Crystal ) pulses DVO 88CU74-9 TMP88CU74 XTIN XTOUT (Open) (d) External oscillator 2007-10-19 2003-02-17 ...
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... DV7CK = 0 DV1CK = 0 DV1CK = fc/2 fc/2 fm Machine cycle counters Divider Divider Selector 88CU74-10 TMP88CU74 ç SLOW, SLEEP Mode DV7CK = 1 (SYSCK = Selector Stand-by controller Watchdog timer Time base ...
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... P22 (XTOUT) pins are used as input/output ports. In the single-clock mode, the machine cycle time is 4/fc [s] (0.32 µ 12.5 MHz fc (TBTCK fc/2 or fc/2 [Hz µ 32.8 kHz Figure 1.4.6 Machine Cycle 88CU74-11 TMP88CU74 (Initial value: **0* ****) R/W (Initial value: 0**0 0***) R 2007-10-19 2003-02-17 ...
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... NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP88CU74 is placed in this mode after reset. 2. IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock) ...
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... Instruc- tion Release input SLOW Instruction mode CPU Core On-chip Peripherals Reset Reset Operate Operate Halt Halt High-frequency Operate (High and/or Low) Halt Low-frequency Low-frequency Halt Halt 88CU74-13 TMP88CU74 STOP1 mode STOP2 mode Machine Cycle Time 4/fc [s] 4/fc [s] 4/fs [s] 2007-10-19 2003-02-17 ...
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... CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (start IDLE1 mode) Operating mode after STOP mode NORMAL 1/2 mode SLOW mode pin output goes low) if both XEN and XTEN are cleared to “0”. 88CU74-14 TMP88CU74 (Initial value: 0000 00**) R/W Return to SLOW mode DV1CK = × ...
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... To reject noise, STOP mode does not start if port P20 is at high F, SINT5 (SYSCR1), 01010000B ; Sets up the level-sensitive release mode. (SYSCR1 Starts STOP mode 88CU74-15 TMP88CU74 STOP pin high. This mode STOP pin input is low. The STOP pin input goes low STOP 2007-10-19 2003-02-17 ...
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... Starts after specified to the edge-sensitive release mode V IH NORMAL Warm-up operation STOP mode is released by the hardware at the rising edge of pin input. STOP 88CU74-16 TMP88CU74 NORMAL operation STOP pin. In the edge-sensitive pin input is high level. STOP STOP operation 2007-10-19 2003-02-17 ...
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... Warming-up Time [ms] Return to SLOW mode DV1CK = 1 31.457 10.486 7.864 2.621 88CU74-17 TMP88CU74 750 250 pin, RESET RESET pin drops below RESET ...
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... Figure 1.4.11 STOP Mode Start/Release 88CU74-18 TMP88CU74 2007-10-19 2003-02-17 ...
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... IDLE mode includes a normal release mode and an interrupt release mode. Selection is made with the interrupt master enable flag (IMF). Releasing IDLE mode returns from IDLE1 to NORMAL1, from IDLE2 to NORMAL2, and from SLEEP to SLOW mode. 88CU74-19 IDLE á Yes Reset No Yes IMF = 1 Yes (Interrupt release mode) TMP88CU74 2007-10-19 2003-02-17 ...
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... IDLE mode. IDLE mode can also be released by inputting low level on the immediately performs the reset operation. After reset, the TMP88CU74 is placed in NORMAL 1 mode. Note: When a watchdog timer interrupt is generated immediately before IDLE mode is started, the watchdog timer interrupt will be processed but IDLE mode will not be started ...
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... Figure 1.4.13 IDLE Mode Start/Release 88CU74-21 TMP88CU74 2007-10-19 2003-02-17 ...
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... PINTTC2: LD (TC2CR), 10H SET (SYSCR2). 5 CLR (SYSCR2). 7 RETI VINTTC2: DL PINTTC2 88CU74-22 TMP88CU74 ; SYSCK ← 1 (switches the main system clock to the low-frequency clock) XEN ← 0 (turns off high-frequency oscillation) ; Sets TC2 mode (timer mode, source clock: fs) ; Sets warming-up time (according to Xtal characteristics) ...
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... Low-frequency clcok Main system clock SYSCK Note 2: SLOW mode can also be released by inputting low level on the RESET pin, which immediately performs the reset operation. After reset, the TMP88CU74 is placed in NORMAL1 mode. Example: Switching from SLOW mode to NORMAL2 mode (fc = 12.5 MHz, warming-up time is 5.8 ms). ...
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... Figure 1.4.14 Switching between the NORMAL2 and SLOW Modes 88CU74-24 TMP88CU74 2007-10-19 2003-02-17 ...
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... Interrupt Controller The TMP88CU74 each have a total of 15 interrupt sources: 6 externals and 9 internals. Nested interrupt control with priorities is also possible. Two of the internal sources are pseudo non-maskable interrupts; the remainder are all maskable interrupts. Interrupt latches (IL) that hold the interrupt requests are provided for interrupt sources. ...
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... The contents of interrupt latches can be read out by an instruction. Therefore, testing interrupt requests by software is possible. Example 1: Clears interrupt latches LDW Example 2: Reads interrupt latches LD Example 3: Tests an interrupt latch TEST JR (ILL), 1110100000111111B ; IL12, IL10 to IL6 ← 0 WA, (ILL ← ILH, A ← ILL (IL). IL7 = 1 then jump F, SSET 88CU74-26 TMP88CU74 2007-10-19 2003-02-17 ...
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... Figure 1.5.1 Interrupt Controller Block Diagram 88CU74-27 TMP88CU74 2007-10-19 2003-02-17 ...
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... Example 1: Sets EF for individual interrupt enable, and sets IMF to “1”. LDW Example 2: Sets an individual interrupt enable flag to “1”. SET (EIRL), 1110100010100001B ; EF15 to EF13, EF11, EF7, EF5, IMF ← 1 (EIRH).4 ; EF12 ← 1 88CU74-28 TMP88CU74 2007-10-19 2003-02-17 ...
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... The instruction stored at the entry address of the interrupt service program is executed IL11 IL10 IL9 IL8 IL7 IL6 IL5 EF9 EF8 EF7 EF6 EF5 88CU74-29 TMP88CU74 IL4 IL3 IL2 ILL (0003CH) (Initial Value: 00000000 000000**) EF4 IMF EIRL (0003AH) (Initial Value: 00000000 0000***0) 2007-10-19 2003-02-17 ...
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... Interrupt acceptance RETI instruction − − − − (b) Return from interrupt instruction 88CU74-30 TMP88CU74 Interrupt service task Instruction n − − − (FFFE7). 3 − 0 ...
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... INT0EN in the external INT0 pin input can not be detected interrupt INT0 LD (EINTCR), 00000000B ; TEST (000F0H JRS T, SINT0 RETI Interrupt processing RETI DL PINT0 88CU74-31 TMP88CU74 Interrupt service program INT0EN ← 0 Return without interrupt processing if (000F0H 2007-10-19 2003-02-17 ...
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... Example: Register save/restore using push and pop instructions PINTxx: PUSH WA Interrupt processing POP WA RETI 88CU74-32 TMP88CU74 ; RBS ← RBS + 1 ; Restores bank and Returns ; Interrupt service routine entry address ; Save WA register pair ; Restore WA register pair ...
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... A, (GSAVA) RETI Main task Switch to bank n by LD, RBS and n instruction Switch to bank n automatically Restore to bank m automatically by [RETI]/[RETN] (b) Saving/restoring using push/pop or data transfer instructions 88CU74-33 TMP88CU74 Address (example) 0023AH 0023B 0023C 0023D 0023E 0023F 00240 00241 At execution of an interrupt return instruction ...
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... The interrupt master enable flag is set to “1” only when a non-maskable interrupt is accepted in interrupt enable status. However, the interrupt master enable flag remains at “0” when so clear by an interrupt service program. 4. The interrupt nesting counter is decremented, and the interrupt nesting flag is changed. 88CU74-34 TMP88CU74 2007-10-19 2003-02-17 ...
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... External Interrupts The TMP88CU74 has six external interrupt inputs ( ). Four of these are equipped with digital noise reject circuits(pulse inputs of less than INT5 a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. The as either an external interrupt input pin or an input/output port, and is configured as an input port during reset ...
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... INT3 INT2 INT1 (Initial value: 00*0 000 Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P10 input/output port 1: pin (Port P10 should be set to an input mode) INT0 0: Rising edge 1: Falling edge 88CU74-36 TMP88CU74 R/W 2007-10-19 2003-02-17 ...
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... Reset Circuit The TMP88CU74 has four types of reset generation procedures: an external reset input, an address trap reset output, a watchdog timer reset output and a system clock reset output. Table 1.6.1 shows on-chip hardware initialization by reset action. The malfunction reset output circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. The “ ...
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... The reset time is about 8/fc to 24/fc [s] (0.64 to 1.92 µs at 12.5 MHz). pin output will go low. The reset time is about 8/fc to 24/fc [s] RESET (“L” output) (H’) 8/fc to 24/fc [s] 4/fc to 12/fc [s] Figure 1.6.2 Address-trap-reset 88CU74-38 TMP88CU74 Reset release Instruction at address r 20/fc [s] RESET 2007-10-19 2003-02-17 ...
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... On-Chip Peripheral Functions 2.1 Special Function Registers (SFR) The TMP88CU74 uses the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function registers (SFR). The SFR are mapped to addresses 00000H to 0003FH, and DBR are mapped to address 00F80H to 00FFFH ...
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... Reserved 00FF7 00FF8 SIO FC transmit data buffer (8 bytes (b) Data Buffer Registers 2.2 I/O Ports The TMP88CU74 each have 11 parallel input/output ports (71 pins) each as follows: 1. Port P0 8-bit I/O port 2. Port P1 8-bit I/O port 3. Port P2 3-bit I/O port 4. Port P3 3-bit I/O port 5. Port P4 8-bit I/O port 6. ...
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... ADD/ADDC/SUB/SUBB/AND/OR/XOR (src (src) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL) 9. MXOR (src), m (b) Instructions that read the pin input data 1. (HL) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src), (HL) Fetch cycle Read cycle (a) Input timing Fetch cycle Write cycle Old New (b) Output timing 88CU74-41 TMP88CU74 2007-10-19 2003-02-17 ...
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... P02 P01 P00 SO1 SI1 SCK1 (Initial value: 0000 0000) 0: Input mode 1: Output mode (P0), 00001010B ; Sets initial data to P0 output latches (P0CR), 00001111B ; Sets the port P0 input/output mode 88CU74-42 TMP88CU74 P00, P01 P02 to P07 Write only 2007-10-19 2003-02-17 ...
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... INT1 (Initial value: 0000 0000) PPG INT0 TC2 (Initial value: 0000 0000) 0: Input mode 1: Output mode (EINTCR), 01000000B ; INT0EN ← 1 (P1), 10111111B ; P17 ← 1, P14 ← 1, P16 ← 0 (P1CR), 11010000B 88CU74-43 TMP88CU74 ) is configured as an input INT0 Write only 2007-10-19 2003-02-17 ...
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... XTEN (00002H) CMP/MCMP/TEST/others P20 ( / INT 5 STOP Osc. enable P21 (XTIN) P22 (XTOUT) Note 1: *: Don’t care Note 2: XTEN is bit 6 in SYSCR2 P22 P21 XTOUT XTIN (Initial value: **** *111) Figure 2.2.4 Port P2 88CU74-44 TMP88CU74 ) 0 P20 INT 5 STOP 2007-10-19 2003-02-17 ...
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... Note 1: *: Don’t care Note P32 P31 P30 (Initial value: **** *000) SCL SDA SCK 0 SI0 SO0 P3O (Initial value: **00 0000) P3CR DR0 0: Input mode 1: Output mode 0: Tri-state 1: Open-drain 88CU74-45 TMP88CU74 P3i Write only 2007-10-19 2003-02-17 ...
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... Note 1: Set the terminal which is used as an analog input to input mode. Note Figure 2.2.6 P4 and Port P4 Control Register P42 P41 P40 (Initial value: 0000 0000 (Initial value: 0000 0000) 0: Input mode 1: Output mode 88CU74-46 TMP88CU74 P4i Write only 2007-10-19 2003-02-17 ...
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... Note 1: Set the terminal which is used as an analog input to input mode. Note Note 3: *: Don’t care Figure 2.2.7 P5 and Port P5 I/O Control Register P52 P51 P50 (Initial value: **** 0000) AIN8 AIN6 (Initial value: **** 0000) 0: Input mode 1: Output mode 88CU74-47 TMP88CU74 P5i Write only 2007-10-19 2003-02-17 ...
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... Data input Data output 7 P6 P67 (00006H) V7 CMP/MCMP/TEST/Others SET/CLR/ CPL/Others D Q P6i Output latch Note VKK P66 P65 P64 P63 P62 P61 (Initial value: 0000 0000) Figure 2.2.8 Port P6 88CU74-48 TMP88CU74 0 P60 V0 2007-10-19 2003-02-17 ...
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... VFT driver output 7 P7 P77 (00007H) V15 CMP/MCMP/TEST/Others SET/CLR/ CPL/Others D Q P7i Output latch Note VKK P76 P75 P74 P73 P72 P71 V14 V13 V12 V11 V10 V9 (Initial value: 0000 0000) Figure 2.2.9 Port P7 88CU74-49 TMP88CU74 0 P70 V8 2007-10-19 2003-02-17 ...
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... P87 (00008H) V23 CMP/MCMP/TEST/Others SET/CLR/ CPL/Others D Q P8i Output latch Note VKK P86 P85 P84 P83 P82 P81 V22 V21 V20 V19 V18 V17 (Initial value: 0000 0000) Figure 2.2.10 Port P8 88CU74-50 TMP88CU74 0 P80 V16 2007-10-19 2003-02-17 ...
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... P9 P97 (00009H) V31 CMP/MCMP/TEST/Others SET/CLR/CPL/Others D Q P9i Output latch Note VKK P96 P95 P94 P93 P92 P91 V30 V29 V28 V27 V26 V25 (Initial value: 0000 0000) Figure 2.2.11 Port P9 88CU74-51 TMP88CU74 0 P90 V24 2007-10-19 2003-02-17 ...
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... PD (0001DH) CMP/MCMP/TEST/Others Data input SET/CLR/ CPL/Others Data output D Q Output latch Note Don’t care PD4 PD3 PD2 PD1 PD0 (Initial value: ***0 0000) V36 V35 V34 V33 V32 Figure 2.2.12 PD Port 88CU74-52 TMP88CU74 PDi VKK 2007-10-19 2003-02-17 ...
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... E detector TBTCK TBTEN TBTCR Time base timer control register (a) Configuration Interrupt period Enable TBT (b) Time base timer interrupt Figure 2.3.1 Time Base Timer 16 [Hz] and enables an INTTBT interrupt. (TBTCR), 00001010B (EIRL). 6 88CU74-53 TMP88CU74 INTTBT interrupt request 2007-10-19 2003-02-17 ...
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... Time Base Timer Interrupt Frequency [Hz] NORMAL1/2, IDLE1/2 Mode DV7CK = 1 DV1CK = 0 DV1CK = 95.37 128 128 381.47 512 512 762.94 1024 1024 2048 2048 4096 4096 16384 16384 88CU74-54 TMP88CU74 (Initial value: 0**0 0***) SLOW, SLEEP DV7CK = 1 mode fs/2 fs R/W fs/2 fs µ fs µ fs µ ...
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... WDTT WDTEN 00034H WDTCR1 Watchdog timer control registers Figure 2.4.1 Watchdog Timer Configuration Binary Counters Overflow WDT output 1 2 Writing Writing WDTOUT disable code clear code Controller 00035H WDTCR2 88CU74-55 TMP88CU74 Reset release R Reset output Q S RESET Interrupt request INTWDT 2007-10-19 2003-02-17 ...
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... CPU malfunction. (WDTCR2), 4EH ; Clears the binary counters (WDTCR1), 00001101B ; WDTT ← 10, WDTOUT ← 1 (WDTCR2), 4EH ; Clears the binary counters (always clear immediately after changing WDTT) (WDTCR2), 4EH ; Clears the binary counters (WDTCR2), 4EH ; Clears the binary counters 88CU74-56 TMP88CU74 2007-10-19 2003-02-17 ...
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... Interrupt request 1: Reset output 4EH: Watchdog timer binary counter clear (clear code) B1H: Watchdog timer disable (disable code) others: Invalid LDW (WDTCR1), 0B101H ; 88CU74-57 TMP88CU74 ç (Initial value: **** 1001) SLOW DV7CK = 1 mode Write only 2 /fs 2 /fs 2 /fs 15 ...
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... SP, 0023FH ; (WDTCR1), 00001000B ; 19 2 / (High-Z) 88CU74-58 TMP88CU74 SLOW Mode 250 ms 62.5 ms Sets the stack pointer WDTOUT ← 0 (WDTT = 11B (“L” output) 2007-10-19 2003-02-17 ...
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... P13 ( ) DVO P13 output latch DVOEN DVOEN pin output DVO (b) Divider output timing chart Figure 2.5.2 Divider Output 88CU74-59 TMP88CU74 ). The P13 output latch DVO (Initial value: 0**0 0***) SLOW, DV7CK = 1 SLEEP R/W mode = = 0 DV1CK fs/2 fs/2 fs ...
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... Timer/Counter 1 (TC1) 2.6.1 Configuration Figure 2.6.1 Timer/Counter 1 (TC1) 88CU74-60 TMP88CU74 2007-10-19 2003-02-17 ...
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... External clock (TC1 pin input) 00: Stop and counter clear 01: Command start 10: Reserved 11: External trigger start Double edge capture 0: Trigger start 0: Pulse 0: Clear 88CU74-61 TMP88CU74 TREG1AL (00010H) Write only TREG1BL (00012H) (Initial value: 0000 0000 ) SLOW, DV7CK = 1 SLEEP ...
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... EF4 ; (TC1CR), 00010000B ; (TC1CR), 01010000B ; WA, (TREG1B) ; 88CU74-62 TMP88CU74 DV7CK = 1 DV1CK = 1 Maximum Resolution Maximum [µs] Time Setting 16.0 s 244.14 µs 16 µs 1.0 s 32. µs 65.5 ms Sets the timer register ÷ ...
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... Capture m (b) Software capture LD (EINTCR), 00000000B ; LDW (TREG1A), 004EH ; SET (EIRL).EF4 ; EI LD (TC1CR), 00111000B ; 88CU74-63 TMP88CU74 − Capture n INT3ES ← 0 (rising edge) 4 100 µs ÷ 2 /fc = 4EH INTTC1 interrupt enable TC1 external trigger start, METT1 = 0 ...
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... Trigger Trigger n−2 Match detect (b) Trigger start and stop (METT1 = 1) 88CU74-64 TMP88CU74 INT2ES ← 1 (“L” level ÷ 28/fc = C3H INTTC1 interrupt enable TC1 external trigger start, METT1 = 1 INT2ES = 0 at the Trigger rising edge INT2ES = 0 at the rising edge n− ...
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... SLOW, SLEEP Mode Match detect (a) Positive logic (at INT3ES = (b) Negative logic (at INT3ES = 1) 88CU74-65 TMP88CU74 INT2ES = 1 at the falling edge 1 2 Counter clear Counter clear Match detect Counter clear 2007-10-19 ...
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... Enables INTTC1 (TC1CR), 00110110B ; Starts TC1 with an external trigger at MCAP1=0 (INTTC1SW Complements INTTC1 service switch F, SINTTC1 (HPULSE), (TREG1BL) ; Reads TREG1B ( (HPULSE + 1), (TREG1BH) (WIDTH), (TREG1BL) ; Reads TREG1B (Period) (WIDTH + 1), (TREG1BH) ; Duty calculation PINTTC1 WIDTH 88CU74-66 TMP88CU74 “H” level pulse width) 2007-10-19 ...
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... LD (P1CR), 00000100B ; LD (TC1CR), 10001011B ; LDW (TREG1A), 07D0H ; LDW (TREG1B), 0190H ; LD (TC1CR), 10011011B ; 88CU74-67 TMP88CU74 Count start (INT3ES = Count start (INT3ES = m − − Capture m 2. Duty measurement output, set the P12 output latch to P12 output latch ← 1 ...
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... Output enable Set Clear Q Toggle Timer F/F1 TC1S clear Figure 2.6.8 Output PPG n n+1 (a) Pulse m 0 n+1 [Application] One shot pulse output (b) Single Output Mode Timing Chart PPG 88CU74-68 TMP88CU74 P12 ( ) pin PPG Command start External trigger start 2007-10-19 2003-02-17 ...
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... S 3 TC2S TC2CK TC2CR TC2 control register Figure 2.7.1 Timer/Counter 2 (TC2) TC2S MPX Clear B Y 16-bit up-counter Source A clock S CMP TREG2 16-bit timer register 2 88CU74-69 TMP88CU74 Match detect INTTC2 interrupt Enable Match detect control TREG2H TREG2L write strobe write strobe 2007-10-19 2003-02-17 ...
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... External clock (TC2 pin input) 0: Stop and counter clear 1: Start >0 at warm-up) 88CU74-70 TMP88CU74 TREG2L (00016H) Write only (Initial value: **00 00*0) SLOW SLEEP DV7CK = 1 mode mode DV1CK = ...
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... EF14 ; (TC2CR), 00101100B ; 88CU74-71 TMP88CU74 DV7CK = 1 DV1CK = 1 Maximum Maximum Resolution Time Setting 18.2 h 1.07 min 0.98 ms 1.07 min 1. 2.1 s µs 32. 65.5 ms µs µ ...
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... Enables INTTC2 interrupt (TC2CR), 00111100B ; Starts TC2 SLOW, SLEEP Mode 4 fs/2 (TREG2), 0056H ; Sets TREG2 (120 ms ÷ 2 (EIRH). EF14 ; Enables INTTC2 interrupt (TC2CR), 00100101B ; Starts TC2 2 n − − − Match detect Counter clear 88CU74-72 TMP88CU74 14 /fc = 0056H 2007-10-19 2003-02-17 ...
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... fc/2 , fc fc SCAP TC3CK TC3S TC3CR TC3 control register TC3S Clear Source clock 8-bit up-counter Capture TREG3B TREG3A 8-bit timer register 3A, B Figure 2.8.1 Timer/Counter 3 (TC3) 88CU74-73 TMP88CU74 INTTC3 interrupt Overflow Comparator TC3M CMP Match Capture 2007-10-19 2003-02-17 ...
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... NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 DV1CK = 0 DV1CK = 1 DV1CK = 0 DV1CK = fc/2 fc/2 fs fc/2 fc/2 fs fc/2 fc/2 fs/2 11 External clock (TC3 pin input) 0: Stop and clear 1: Start 0: 1: Software capture trigger 88CU74-74 TMP88CU74 SLOW, SLEEP mode 4 4 fs/2 fs/2 Write 2 fs/2 only 8 fs/2 2007-10-19 2003-02-17 ...
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... LD (TREG3A), 19H ; LD (TC3CR), 00011110B ; Maximum Applied Frequency [Hz] SLOW, SLEEP Mode 4 4 fs/2 88CU74-75 TMP88CU74 DV7CK = 1 DV1CK = 1 Maximum Maximum Resolution Setting Time Setting Time [µs] [ms] [ms] 124.5 488.28 124.5 31.1 122.07 31.1 2.0 16 4.1 0.5 s ÷ 1/ 19H Starts TC3 2007-10-19 ...
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... Up-counter 1 k− − 2 TC3 pin input TREG3A k TREG3B Capture INTTC3 interrupt Reading TREG3A Figure 2.8.3 Capture Mode Timing Chart (at INT4ES = m−1 m+1 n− Capture 88CU74-76 TMP88CU74 . Also, after (Overflow) FE Overflow 2007-10-19 2003-02-17 ...
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... TC4 control register 8-bit timer register 4 Clear Overflow 8-bit up-counter Comparator Match CMP Toggle Set Clear A B TREG4 Y S PWM output mode INTTC4 TC4M interrupt Figure 2.9.1 Timer/Counter 4 (TC4) 88CU74-77 TMP88CU74 Timer F/F4 / PWM 4 PDO 4 Toggle pin Set Q Clear Decoder 2 TFF4 1 2007-10-19 2003-02-17 ...
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... Pulse width modulation (PWM) output mode NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 DV1CK = 0 DV1CK = 1 DV1CK = fc/2 fc/2 fs fc/2 fc/2 fc fc/2 fc/2 fc/2 11 Reserved 0: Stop and counter clear 1: Start 00: Clear 01: Reserved 10: Reserved 11: (Note 3) 88CU74-78 TMP88CU74 SLOW, SLEEP mode DV1CK = fs/2 fs/2 Write 8 fc/2 only 4 fc/2 2007-10-19 2003-02-17 ...
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... PDO (P1 (P1CR), 00010000B ; (TREG4), 5FH ; (TC4CR), 00010010B ; 88CU74-79 TMP88CU74 DV7CK = 1 DV1CK = 1 Maximum Maximum Resolution Setting Time [µs] [s] [s] 62.2 ms 244.14 µs 62.2 ms 2.6 ms 20.48 µs 5.2 ms 163.2 µs 1.28 µs 326 µs P14 output latch ← 1 ...
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... Overwrite 1 cycle NORMAL1/2, IDLE1/2 Mode DV1CK = 1 DV1CK = 0 Repeat Resolution Repeat [µs] Cycle [ms] [µs] Cycle [ms] 83.6 ms 244.14 µs 62.5 ms • 5.2 ms • 1.28 µs 326 µs 88CU74-80 TMP88CU74 − 1 m/m Shift DV7CK = 1 DV1CK = 1 Resolution Repeat [µs] Cycle [ms] 244.14 µs 62.5 ms • • • • • ...
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... Serial Bus Interface (SBI-ver.C) The TMP88CU74 has a 1-channel serial bus interface which employs a clocked-synchronous 8-bit serial bus interface and an I The serial bus interface is connected to an external device through P31 (SDA) and P30 (SCL) in the I C bus mode; and through P32 ( 2 clocked-synchronous 8-bit SIO mode ...
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... A R Data C S Slave address / more bits bits A A Data C Data more 2 C Bus Mode 88CU74-82 TMP88CU74 bits Data more P 2007-10-19 2003-02-17 ...
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... I 2 CAR Slave address (0022H) SA6 SA5 SA4 TMP88CU74 slave address SA selection Address recognition mode ALS specification Note CAR is write-only register, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc. Figure 2.10.3 Serial Bus Interface Control Register 1, Serial Bus Interface Data Buffer Register and ...
Page 84
... Slave address unmatch or “GENERAL CALL” undetected 1: Slave address match or “GENERAL CALL” detected 0: “GENERAL CALL” undetected 1: “GENERAL CALL” detected 0: Last received bit “0” 1: Last received bit “1” 88CU74-84 TMP88CU74 (Initial value: 0001 00**) Write only (Initial value: 0001 0000) Read only ...
Page 85
... In the receiver mode during the clock pulse cycle, the SDA pin is set to the low level in order to generate the acknowledge signal. In non-acknowledge mode, the TMP88CU74 does not count a clock pulse for the acknowledge signal when operating in the slave mode. ...
Page 86
... Master/slave selection Set the MST (bit 7 in SBICR2) to “1” for operating the TMP88CU74 as a master device. Reset the MST for operation as a slave device. The MST is cleared to “0” by the hardware after a stop condition on the bus is detected or arbitration is lost ...
Page 87
... Transmitter/Receiver selection Set the TRX (bit 6 in SBICR2) to “1” for operating the TMP88CU74 as a transmitter. Reset the TRX for operation as a receiver. When data with an addressing format is transferred in the slave mode, the TRX is set to “1” if the direction bit (R/ the master device is “1”, and is cleared to “0” if the bit is “0”. In the master mode, after an acknowledge signal is returned from the slave device with the hardware, the TRX is set to “ ...
Page 88
... SDA pin and the SCL pin in order not to effect data transmitted from other masters with arbitration. When more than one master sends the same data at the first word, arbitration occurs continuously after the second word. 88CU74-88 C bus mode. C bus. 2 TMP88CU74 . LOW C bus 2 2007-10-19 2003-02-17 ...
Page 89
... SDA (Bus) The TMP88CU74 compares levels of the SDA line of the bus with those of the TMP88CU74 SDA pin at the rising edge of the SCL line. If the levels are unmatched, arbitration is lost and the AL (bit 3 in SBISR) is set to “1”. When the AL is set to “1”, the MST and TRX are reset to “0” and the mode is switched to a slave receiver mode. The AL is reset to “ ...
Page 90
... SWRST (bit 0 in SBICR) is set to “1”, internal reset signal pulse is generated and inputted into SBI circuit. All command registers and status registers are initialized to an initial value. SWRST is automatically cleared to “0” after initializing SBI circuit. 88CU74-90 TMP88CU74 2007-10-19 2003-02-17 ...
Page 91
... Figure 2.10.11 Start Condition Generation and Slave Address Transfer CAR. Clear the ALS to “0” to set the bus standard) after setting of the slave Slave address + direction bit 88CU74-91 TMP88CU74 Acknowledge signal from a slave device 2007-10-19 2003-02-17 ...
Page 92
... ACK to “1” and read the received data from the SBIDBR (data which is read immediately after a slave address is sent is undefined). After the data is read, the PIN becomes “1”. The TMP88CU74 outputs a serial clock pulse to the SCL to transfer new 1-word of data and sets the SDA pin to “0” at the acknowledge signal timing. An INTSBI interrupt request occurs and the PIN becomes “ ...
Page 93
... After the data is transmitted and an interrupt request has occurred, set the BC to “001” and read the data. The TMP88CU74 generates a clock pulse for a 1-bit data transfer. Since the master device is a receiver, the SDA line of the bus keeps the high level. The transmitter receives the high-level signal as an ACK signal ...
Page 94
... GENERAL CALL of 1 1/0 which the value of the direction bit sent from the master is “0” the slave receiver mode, the TMP88CU74 0 1/0 terminates receiving of 1-word data. (4) Stop condition generation When the BB is “1”, a sequence of generating a stop condition is started by writing “ ...
Page 95
... Check the BB until it becomes “0” to check that the SCL pin of theTMP88CU74 is released. Check the LRB until it becomes “1” to check that the SCL line of a bus is not pulled down to the low level by other devices ...
Page 96
... Reserved “1” SIOF SEF “1” “1” operating 0 : Transfer terminated 1 : Transfer in process 0 : Shift operation terminated 1 : Shift operation in process 88CU74-96 TMP88CU74 (Initial value: 0000 *000) Write only pin) SCK pin) R/W (Initial value: **** 00**) Write only Read only 2007-10-19 2003-02-17 ...
Page 97
... SCK0 automatic-wait function pin is used as the serial clock. In order SCK0 t SCKH Note: tcyc = 4/fc (in NORMAL mode, IDLE mode) 88CU74-97 TMP88CU74 pin becomes a high 2007-10-19 2003-02-17 ...
Page 98
... Bit 2 Bit 3 Bit 4 Bit 5 **765432 ***76543 ****7654 *****765 Bit 2 Bit 3 Bit 4 Bit 5 10****** 210***** 3210**** 43210*** 543210** after the SIOF goes “1”. SCK 88CU74-98 TMP88CU74 Bit 6 Bit 7 ******76 *******7 Bit 6 Bit 7 6543210* 76543210 *: Don’t care 2007-10-19 2003-02-17 ...
Page 99
... External clock Figure 2.10.21 Transfer Mode TEST (SBISR). SEF ; JRS F, STEST1 TEST (P3 JRS T, STEST2 LD (SBICR1), 00000111B ; 88CU74-99 TMP88CU74 SEF = 1 then loop then loop SCK SIOS ← 0 ...
Page 100
... Note: When the transfer mode is switched, the SBIDBR contents are lost. In case that the mode needs to be switched, conclude receiving data by clearing the SIOS to “0”, read the last data, and then switch the mode. 88CU74-100 Bit7 t = 3.5/fc [s] (min) (In NORMAL mode, IDLE mode) SODH TMP88CU74 2007-10-19 2003-02-17 ...
Page 101
... SIOS to “0”, read the last data, and then switch the transfer mode Read received data after the SIOF goes “1”. SCK 88CU74-101 TMP88CU74 Clear SIOS Read received data 2007-10-19 2003-02-17 ...
Page 102
... Read received Write transmitted data (c) data (b) Bit 7 in last transmitted word t = Min 4/fc [s] (In NORMAL mode, IDLE mode) SODH 88CU74-102 TMP88CU74 Clear SIOS ...
Page 103
... Serial Interface (SIO1) The TMP88CU74 has clocked-synchronous 8-bit serial interfaces (SIO1). The serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer bits of data. The serial interface is connected to external devices via pins P02 (SO1), P01 (SI1), P00 ( ) for SIO1 ...
Page 104
... TMP88CU74 (Initial value: 0000 0000) Write only SLOW, SLEEP DV7CK = 1 mode fs/2 fs/2 ...
Page 105
... Shift operation in process pin goes high when transfer starts. SCK1 SLOW, SLEEP fc = 12.5 MHz mode DV1CK = fs/2 [Hz] fs/2 [Hz] 1.50 Kbit/s 9 • fc/2 48.8 7 • fc/2 185 6 • fc/2 390 88CU74-105 TMP88CU74 Read only Maximum transfer rate fs = 32.768 KHz 1 Kbit/s • • • Note: 1 Kbit = 1024 bits 2007-10-19 2003-02-17 ...
Page 106
... Received data are shifted on the trailing edge of the serial clock (rising edge of the pin input/output). SCK1 88CU74-106 Automatically wait function pin is used as the serial clock. In this SCK1 t SCKH Note: tcyc = 4/fc (In NORAML1/2, IDLE1/2 modes) 4/fs (In SLOW, SLEEP modes) TMP88CU74 2007-10-19 2003-02-17 ...
Page 107
... An INTSIO interrupt is generated when the specified number of words has been transferred. If the number of words changed during transfer, the serial interface must be stopped before making the change. Bit 1 Bit 2 Bit 3 *321 **32 ***3 Bit 1 Bit 2 Bit 3 10** 210* 3210 88CU74-107 TMP88CU74 *: Don’t care 2007-10-19 2003-02-17 ...
Page 108
... TMP88CU74 2007-10-19 2003-02-17 ...
Page 109
... Figure 2.11.8 Transfer Mode (Example: 8-Bit, 1 Word Transfer (a) Internal clock Clear SIOS (b) External clock 88CU74-109 TMP88CU74 Clear SIOS 2007-10-19 2003-02-17 ...
Page 110
... Note: The buffer contents are lost when the transfer mode is switched should become necessary to switch the transfer mode, end receiving by clearing SIOS to “0”, read the last data and then switch the transfer mode 88CU74-110 Bit7 t = 3.5/fc [s] (min) (In the NORMAL1/2, IDLE1/2 modes) SODH = 3.5/fs [s] (min) (In the SLOW, SLEEP modes) TMP88CU74 õ 2007-10-19 2003-02-17 ...
Page 111
... SIOS to “0”, read the last data and then switch the transfer mode Read out 88CU74-111 TMP88CU74 Clear SIOS Read out 2007-10-19 2003-02-17 ...
Page 112
... Read out (c) Write (b) Bit7 t SODH t = 4/fc [s] (min) (In the NORMAL1/2, IDLE1/2 modes) SODH = 4/fs [s] (min) (In the SLOW, SLEEPmodes) 88CU74-112 TMP88CU74 Clear SIOS Read out (d) ...
Page 113
... AD Converter (ADC) The TMP88CU74 each have an 8-channel multiplexed-input 12-bit successive approximate type AD converter with sample and hold. 2.12.1 Configuration R/2 VAREF STOP AINDS Analog input multiplexer AIN0 A Y AIN1 AIN10 K AIN11 P4CR, P5CR P4, P5 input/output control register 2.12.2 Control The AD converter is controlled by the AD converter control register (ADCCR) ...
Page 114
... AIN6 select 1110: Reserved 0111: AIN7 select 1111: Reserved 0: Enable 1: Disable 0: 184/fc [s]: 23 µs ( MHz) 1: 736/fc [s]: 59 µs (fc = 12.5 MHz) 0: conversion start 0: Under conversion or Before conversion 1: End of conversion 88CU74-114 TMP88CU74 (Initial value: 0000 0000) R/W Read only 2007-10-19 2003-02-17 ...
Page 115
... Figure 2.12.4 AD Conversion Timing Chart (ACK = 1) Example: ; AIN SELECT CONVERT START SET SLOOP: TEST JRS ; RESULT DATA READ LD 88CU74-115 Result Invalid Invalid Conversion time 736/fc [s] (ADCCR), 00100100B ; Selects AIN4, ACK = 1 (ADCCR ADS = 1 (ADCCR EOCF = SLOOP (9EH), (ADCDR) TMP88CU74 Result 2007-10-19 2003-02-17 ...
Page 116
... FFH FEH FDH 03H 02H 01H 253 Analog input voltage Figure 2.12.5 Analog Input Voltage vs AD Conversion Result (typ.) 88CU74-116 VAREF − VASS × 254 255 256 256 TMP88CU74 2007-10-19 2003-02-17 ...
Page 117
... Vacuum Fluorescent Tube (VFT) Driver Circuit The TMP88CU74 features built-in high-breakdown voltage output buffers for directly driving fluorescent tubes, and a display control circuit used to automatically transfer display data to the output port. The segment and the digit the VFT drive circuit which included in the usual products, are not allocated ...
Page 118
... Display data memory (112 bytes in DBR T15 High-breakdown voltage output Figure 2.13.1 Vacuum Fluorescent Tube (VFT) Driver Circuit Internal data bus Display control register 1 Display control register 2 VFT timing generator Output data latch V34 V35 V36 88CU74-118 TMP88CU74 fc 2007-10-19 2003-02-17 ...
Page 119
... V0) 00001: 33 (V32 to V0) 00010: 34 (V33 to V0) 00011: 35 (V34 to V0) 00100: 36 (V35 to V0) 00101: 37 (V36 to V0) 88CU74-119 TMP88CU74 (Initial value: 0000 0000) DV1CK = /fc Write only 2007-10-19 2003-02-17 ...
Page 120
... T0) 1101: 14 display mode (T13 to T0) 1110: 15 display mode (T14 to T0) 1111: 16 display mode (T15 to T0 VFT display in operation 1: VFT display operation disabled 88CU74-120 TMP88CU74 (Initial value: 000* 0000) Write only Read only 2007-10-19 2003-02-17 ...
Page 121
... V16 to V23 V24 to V31 V32 to V36 88CU74-121 TMP88CU74 Timing T10 T11 T12 T13 T14 T15 2007-10-19 2003-02-17 ...
Page 122
... MSB LSB SEG * * SEG * * SEG * * SEG * * SEG * * SEG MSB * * SEG (Write change by display data) Figure 2.13.6 Example of Conventional Type VFT Driver Pulse 88CU74-122 TMP88CU74 2007-10-19 2003-02-17 ...
Page 123
... When a part used as the input/output pin (VFT driver in operation), the data buffer memory (DBR) of the segment which is also used as the input/output pin must be cleared to “0” (RK = typ. 80 kΩ), it must be KK 88CU74-123 TMP88CU74 2007-10-19 2003-02-17 ...
Page 124
... However it is necessary to drive R down to pin VDD (a) At output Figure 2.13.8 External Circuit Interface 88CU74-124 KK voltage applying to the external circuit. KK (typ. 80 kΩ) sufficiently because of pulled K VDD (b) At input TMP88CU74 is used as usual is pin 2007-10-19 2003-02-17 ...
Page 125
... Input/Output Circuitry (1) Control pins The input/output circuitries of the TMP88CU74 control pins are shown below. Control Pin I/O Osc. enable VDD XIN Input XOUT Output Osc. enable VDD XTIN Input XTOUT Output Address-trap-reset RESET I/O Watchdog-timer-reset System-clock-reset / STOP INT 5 Input TEST Input Note: The TEST pin of the TMP88PU74 does not have a pull-down resistor. Fix the test pin at low-level ...
Page 126
... VDD R VDD R R VDD R VDD R VDD VKK R1 88CU74-126 TMP88CU74 Remarks Tri-state I/O Hysteresis input kΩ (typ.) Tri-state I kΩ (typ.) Sink open drain output Hysteresis input kΩ Tri-state I/O Hysteresis input ProgrammableKOpen-drain kΩ (typ.) Tri-state I kΩ (typ.) Source open drain I/O ...
Page 127
... Input/Output ports Port I/O PD I/O Input/Output Circuitry Initial “High-Z” VDD VKK R1 88CU74-127 TMP88CU74 Remarks Source open drain I/O High-breakdown voltage kΩ (typ kΩ (typ 200 kΩ (typ.) 2007-10-19 2003-02-17 ...
Page 128
... SLEEP modes 32.768 KHz STOP modes V ≥ 4 < 4 ≥ 4 < 4 4.5 to 5.5 V (Note 2 88CU74-128 TMP88CU74 Ratings Unit −0.3 to 6.5 −0 0 −0 0.3 DD − 0 3.2 −25 mA −40 120 −160 1200 mW 260 (10 s) °C − 125 − ...
Page 129
... How to Calculate Power Consumption. With the TMP88CU74, a pull-down resistor (R using mask option (port by port). The share of VFT driver loss (VFT driver output loss + pull-down resistor (R ) loss) in power consumption Pmax is high. When using a fluorescent display tube with K a large number of segments, the maximum power consumption P ...
Page 130
... 4.5 to 5.5 V, Topr = −30 to 70° Conditions Min 5 0.0 V AREF ASS 5.000 V AREF V = 0.000 V ASS 88CU74-130 TMP88CU74 Min Typ. Max Unit 0.9 V ±2 µA 100 220 450 kΩ 110 2 ...
Page 131
... Oscillation Recommended Oscillator Frequency 12.5 MHz Murata CSA12.5MTZ 8 MHz Murata CSA8.00MTZ 12.5 MHz NDK AT-51 32.768 kHz NDK MX-38T XTIN (2) Low-frequency Oscillation 88CU74-131 TMP88CU74 Typ. Max Unit 10 µs 133.3 ns µs Recommended Constant ...
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... TMP88CU74 2007-10-19 2003-02-17 ...