tmp88cu74 TOSHIBA Semiconductor CORPORATION, tmp88cu74 Datasheet - Page 61

• Manufacturer Part Number: tmp88cu74
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.6.2
(00010, 00011H)
(00012, 00013H)
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]
Note 2: Writing to the lower byte of the timer registers (TREG1AL, TREG1BL), the comparison is inhibited until the upper
Note 3: Set the mode, source clock, edge (including INT2ES), PPG control and timer F/F control when TC1 stops
Note 4: Software capture can be used in only timer and event counter modes. SCAP1 is automatically cleared to “0” after
Note 5: Values to be loaded to timer registers must satisfy the following condition.
Note 6: Always write “0” to TFF1 except PPG output mode.
Note 7: TC1CR and TREG1A are write-only registers and must not be used with any of the read-modify-write instructions
Note 8: Writing to the TREG1B is not possible unless TC1 is set to the PPG output mode.
Note 9: Please use the auto-capture function in the operative condition of TC1.
Note 10:Since the up-counter value is captured into TC1DRB by the source clock of up-counter after
Control
(00014H)
TREG1A
TREG1B
TC1CR
byte(TREG1AH, TREG1BH) is written. Only the lower byte of the timer registers can not be changed. After
writing to the upper byte, any match during 1 machine cycle (instruction execution cycle) is ignored.
(TC1S = 00).
capturing.
such as SET, CLR, etc.
A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture
disable. Please read the capture value in a capture enabled condition.
setting TC1CR<ACAP1> to “1”. Therefore, wait at least one cycle of the internal source clock
before reading TC1DRB for the first time.
TREG1A>TREG1B>0(PPG output mode), TREG1A>0 (others)
16-bit timer registers (TREG1A and TREG1B). Reset does not affect TREG1A and
TREG1B.
MCAP1
MPPG1 PPG output control
TC1CK
SCAP1
METT1
TC1M
The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and two
TFF1
TC1S
15
TFF1
7
14
TC1 source clock select [Hz]
TC1 start control
Software capture control
Pulse width measurement
mode control
External trigger timer mode
control
Time F/F1 control for PPG
output mode
MPPG1
SCAP1
MCAP1
METT1
TC1 operating mode select
Figure 2.6.2 Timer Registers and TC1 Control Register
6
13
TREG1BH (00013H)
TREG1AH (00011H)
5
12
TC1S
11
4
88CU74-61
10
00: Timer/external trigger timer/event counter mode
01: Window mode
10: Pulse width measurement mode
11: PPG (Programmable pulse generate) output mode
00: Stop and counter clear
01: Command start
10: Reserved
11: External trigger start
0: +
0: Double edge capture
0: Trigger start
0: Pulse
0: Clear
00
01
10
11
3
TC1CK
9
DV1CK = 0
fc/2
fc/2
fc/2
Read/Write (Writing is capable only when PPG output mode)
2
11
8
7
3
DV7CK = 0
NORMAL1/2, IDLE1/2 mode
7
DV1CK = 1
1
fc/2
External clock (TC1 pin input)
fc/2
fc/2
TC1M
12
8
4
6
0
1: Software capture trigger
1: Single edge capture
1: Trigger start & stop
1: Single
1: Set
DV1CK = 0
Write only
5
TREG1AL (00010H)
TREG1BL (00012H)
(Initial value: 0000 0000 )
fs/2
fc/2
fc/2
3
7
3
DV7CK = 1
4
DV1CK = 1
3
fs/2
fc/2
fc/2
3
8
4
2
TMP88CU74
SLOW,
SLEEP
mode
fs/2
2007-10-19
+
+
1
3
Write
only
0