tmp88cu74 TOSHIBA Semiconductor CORPORATION, tmp88cu74 Datasheet - Page 29

• Manufacturer Part Number: tmp88cu74
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

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IL
EIR
(0003C, 0003DH)
(0003A, 0003BH)
1.5.1
Note 1: Do not use any read-modify-write instruction such as bit manipulation for clearing IL.
Note 2: Do not set IMF to “1” during non-maskable interrupt service program.
Note 3: Bits1 and 0 in ILL are read in as undefined data when a read instruction is executed.
Note 4: *: Don’ t care
EF15 EF14 EF13 EF12 EF11 EF10
IL15
Interrupt Sequence
cleared to “0” by a reset or an instruction. Interrupt acceptance sequence requires 12
machine cycles (3.84 µs at fc = 12.5 MHz in the NORMAL mode) after the completion of the
current instruction execution. The interrupt service task terminates upon execution of an
interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for pseudo
non-maskable interrupts). Figure 1.5.3 shows the timing chart of interrupt acceptance
processing.
(1) Interrupt acceptance
15
An interrupt request is held until the interrupt is accepted or the interrupt latch is
1.
2.
3.
4.
5.
6.
IL14
14
Interrupt acceptance processing is as follows.
Figure 1.5.2 Interrupt latch (IL) and interrupt enable register (EIR)
acceptance of any following maskable interrupts. When a non-maskable interrupt
is accepted, the acceptance of any following interrupts is temporarily disabled.
The contents of the program counter (return address) and the program status
word (PSW) are saved (pushed) on the stack in sequence of PSWH, PSWL, PCE,
PCH, PCL. The stack pointer (SP) is decremented five times.
The entry address of the interrupt service program is read from the vector table,
and set to the program counter.
added to the RBS.
The instruction stored at the entry address of the interrupt service program is
executed.
The interrupt master enable flag (IMF) is cleared to “0” to temporarily disable the
The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.
The RBS control code is read from the vector table. The lower 4-bit of this code is
IL13
13
ILH (0003DH)
EIRH (0003BH)
IL12
12
IL11
11
IL10
10
88CU74-29
EF9
IL9
9
EF8
IL8
8
EF7
IL7
7
EF6
IL6
6
EF5
IL5
5
EIRL (0003AH)
ILL (0003CH)
EF4
(Initial Value: 00000000 000000**)
IL4
(Initial Value: 00000000 0000***0)
4
IL3
3
IL2
2
TMP88CU74
1
2007-10-19
2003-02-17
IMF
0