tmp88cu74 TOSHIBA Semiconductor CORPORATION, tmp88cu74 Datasheet - Page 19
tmp88cu74
Manufacturer Part Number
tmp88cu74
Description
Cmos 8-bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88CU74.pdf
(132 pages)
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(2) IDLE mode (IDLE1, IDLE2, SLEEP)
interrupts. The following status is maintained during IDLE mode.
is made with the interrupt master enable flag (IMF). Releasing IDLE mode returns
from IDLE1 to NORMAL1, from IDLE2 to NORMAL2, and from SLEEP to SLOW
mode.
1.
2.
3.
IDLE mode is controlled by the system control register 2 (SYSCR2) and maskable
IDLE mode includes a normal release mode and an interrupt release mode. Selection
Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals
continue to operate.
The data memory, CPU registers, program status word and port output latches
are all held in the status in effect before IDLE mode was entered.
The program counter holds the address of the second instruction after the
instruction which starts IDLE mode.
Example: Starting IDLE mode.
(Normal release mode)
SET
No
No
Figure 1.4.12 IDLE Mode
Execution of the instruction
which follows the IDLE
CPU, WDT are halted
mode start instruction
Starting IDLE mode
Interrupt processing
(SYSCR2). 4
Interrupt request
88CU74-19
by instruction
Reset input
IMF = 1
No
Yes
Yes
(Interrupt release mode)
Yes
Reset
;
IDLE á 1
TMP88CU74
2007-10-19
2003-02-17
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