tmp88cu74 TOSHIBA Semiconductor CORPORATION, tmp88cu74 Datasheet - Page 86

• Manufacturer Part Number: tmp88cu74
• Description: Cmos 8-bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SCL pin (Master 1)
SCL pin (Master 2)
SCL (Bus)
(4) Slave address and address recognition mode specification
(5) Master/slave selection
the slave address, clear the ALS (bit 0 in I
I
the slave address, set the ALS to “1”. With a free data format, the slave address and the
direction bit are not recognized, and they are processed as data from immediately after
start condition.
device.
hardware after a stop condition on the bus is detected or arbitration is lost.
b.
2
CAR) to the slave address.
When the serial bus interface circuit is used with an addressing format to recognize
When the serial bus interface circuit is used with a free data format not to recognize
Set the MST (bit 7 in SBICR2) to “1” for operating the TMP88CU74 as a master
Reset the MST for operation as a slave device. The MST is cleared to “0” by the
which pulls down a clock pulse to low will, in the first place, invalidate a clock
pulse of another master device which generates a high-level clock pulse. The
master device with a high-level clock pulse needs to detect the situation and
implement the following procedure.
even when more than one master exists on a bus.
simultaneously exist on a bus.
the bus becomes the low level. After detecting this situation, Master 2 resets
counting a clock pulse in the high level and sets the SCL pin to the low level.
SCL pin to the high level. Since Master 2 holds the SCL line of the bus at the low
level, Master 1 waits for counting a clock pulse in the high level. After Master 2
sets a clock pulse to the high level at point “c” and detects the SCL line of the bus
at the high level, Master 1 starts counting a clock pulse in the high level.
high-level period and the master device with the longest low-level period from
among those master devices connected to the bus.
Clock synchronization
In the I
The TMP88CU74 has a clock synchronization function for normal data transfer
The example explains clock synchronization procedures when two masters
As Master 1 pulls down the SCL pin to the low level at point “a”, the SCL line of
Master 1 finishes counting a clock pulse in the low level at point “b” and sets the
The clock pulse on the bus is deteminded by the master device with the shortest
2
C bus mode, in order to drive a bus with a wired AND, a master device
a
Figure 2.10.6 Clock Synchronization
Count reset
88CU74-86
b
Wait
c
Count start
2
CAR) to “0”, and set the SA (bits 7 to 1 in
Count reset
TMP88CU74
2007-10-19
2003-02-17