tmp88cu74 TOSHIBA Semiconductor CORPORATION, tmp88cu74 Datasheet - Page 79
tmp88cu74
Manufacturer Part Number
tmp88cu74
Description
Cmos 8-bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP88CU74.pdf
(132 pages)
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Table 2.9.1 Source Clock (Internal clock) for Timer/Counter 4 (Example: at fc = 12.5 MHz, fs = 32.8 kHz)
TC4CK
TC4CK
00
01
10
00
01
10
INTTC4 interrupt
PDO
Internal clock
4
Up-counter
Timer F/F4
(2) Programmable divider output (PDO) mode
Resolution
163.84 µs
pin output
Resolution
244.14 µs
10.24 µs
TREG4
0.64 µs
[µs]
SLOW, SLEEP Mode
[µs]
the contents of the up-counter. If a match is found, the timer F/F 4 output is toggled
and the counter is cleared. Timer F/F 4 output is inverted and output to the P14
(
“1”. This mode can be used for approximate 50% duty pulse output. Timer F/F 4 can be
initialized by program, and it is initialized to “0” during reset. An INTTC4 interrupt is
generated each time the
PPO4
DV1CK = 0
The internal clock is used for counting up. The contents of TREG4 are compared with
Example: Output a 1024 Hz pulse (at fc = 12.5 MHz)
Setting Time
) pin. When programmable divider output is executed, P14 output latch is set to
0
163.2 µs
Maximum
41.7 ms
Setting Time
n
2.6 ms
Maximum
[s]
1
Match detect
62.2 ms
DV7CK = 0
[s]
2
Figure 2.9.3 PDO Mode Timing Chart
SET
LD
LD
LD
327.68 µs
Resolution
20.48 µs
1.28 µs
[µs]
n 0
DV1CK = 1
PDO
1
(P1). 4
(P1CR), 00010000B
(TREG4), 5FH
(TC4CR), 00010010B
88CU74-79
NORMAL1/2, IDLE1/2 Mode
Setting Time
Maximum
output is toggled.
326
83.6 ms
2
5.2 ms
[s]
µs
n 0
Resolution
244.14 µs
10.24 µs
0.64 µs
1
[µs]
DV1CK = 0
2
;
;
;
;
Setting Time
163.2 µs
Maximum
Set output mode to P14
1/1024 ÷ 2
Starts TC4
P14 output latch ← 1
62.2 ms
2.6 ms
n 0
[s]
DV7CK = 1
1
7
/fc = 5FH
2
Resolution
244.14 µs
20.48 µs
1.28 µs
[µs]
DV1CK = 1
n 0
TMP88CU74
2007-10-19
2003-02-17
Setting Time
326
62.2 ms
Maximum
5.2 ms
1
[s]
µs
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