p89v660 NXP Semiconductors, p89v660 Datasheet
p89v660
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p89v660 Summary of contents
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... B/1 kB/2 kB RAM, dual I Rev. 02 — 29 January 2008 1. General description The P89V660/662/664 are 80C51 microcontrollers with 16 kB/32 kB/64 kB flash and 512 B/1 kB data RAM. These devices are designed to be drop-in and software compatible replacements for the P89C660/662/664 devices. Both the In-System Programming (ISP) and In-Application Programming (IAP) boot codes are upward compatible ...
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... I Smaller block sizes. The smallest block size on the P89C660/662/664 devices was 8 kB. The P89V660/662/664 devices have a page size of 128 B. These small pages can be erased and reprogrammed using IAP function calls making use of the code memory for non-volatile data storage practical. Each page erase less. The IAP and ISP code in P89V660/662/664 devices support these 128-byte page operations ...
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... HIGH PERFORMANCE 80C51 CPU 16 kB/32 kB/64 kB CODE FLASH internal bus 0.5 kB/1 kB DATA RAM PORT 4 PORT 3 PORT 2 PORT 1 PORT 0 OSCILLATOR Rev. 02 — 29 January 2008 P89V660/662/664 Temperature range Frequency + MHz to 40 MHz TXD UART RXD SPICLK MOSI SPI MISO SS TIMER 0 T0 ...
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... Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual I P1[5]/CEX2 7 P1[6]/SCL 8 9 P1[7]/SDA RST 10 P3[0]/RXD 11 P89V660/662/664 P4[3]/ P3[1]/TXD P3[2]/INT0 14 P3[3]/INT1 15 16 P3[4]/T0/CEX3 17 P3[5]/T1/CEX4 Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI 39 P0[4]/AD4 38 P0[5]/AD5 37 P0[6]/AD6 36 P0[7]/AD7 P4[1]/SDA_1/MISO 33 ALE/PROG 32 PSEN 31 P2[7]/A15 30 P2[6]/A14 29 P2[5]/A13 002aab909 © ...
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... Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual I P1[5]/CEX2 1 P1[6]/SCL 2 3 P1[7]/SDA RST 4 P3[0]/RXD 5 P89V660/662/664 P4[3]/ P3[1]/TXD P3[2]/INT0 8 P3[3]/INT1 9 10 P3[4]/T0/CEX3 11 P3[5]/T1/CEX4 Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI 33 P0[4]/AD4 32 P0[5]/AD5 31 P0[6]/AD6 30 P0[7]/AD7 P4[1]/SDA_1/MISO 27 ALE/PROG 26 PSEN 25 P2[7]/A15 24 P2[6]/A14 23 P2[5]/A13 002aab910 © ...
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... CEX0 — Capture/compare external I/O for PCA Module 0. Each capture/compare module connects to a Port 1 pin for external I/O. When not used by the PCA, this pin can handle standard I/O. Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI ) because of the internal IL © NXP B.V. 2008. All rights reserved. ...
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... As inputs, Port 3 pins that are externally pulled LOW will source current (I ) because of the internal pull-ups P3[0] — Port 3 bit 0. I RXD — Serial input port. O P3[1] — Port 3 bit 1. O TXD — Serial output port. Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI © NXP B.V. 2008. All rights reserved ...
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... I External Access Enable: EA must be connected to V order to enable the device to fetch code from the external program memory. EA must be strapped to V program execution. Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI 2 C-bus serial clock input/output 2 C-bus serial data input/output ...
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... O Crystal 2: Output from the inverting oscillator amplifier. I Power supply I Ground 1 of crystal frequency. 3 Rev. 02 — 29 January 2008 P89V660/662/664 [1] is emitted [2] the crystal frequency and can be used for 6 , e.g., for ALE pin. DD © NXP B.V. 2008. All rights reserved. ...
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... P89V660_662_664_2 Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual I Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI © NXP B.V. 2008. All rights reserved ...
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Table 4. Special function registers * indicates Special Function Registers (SFRs) that are bit addressable. Name Description Bit address ACC* Accumulator AUXR Auxiliary function register AUXR1 Auxiliary function register 1 Bit address B* B register CCAP0H Module 0 Capture HIGH ...
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Table 4. Special function registers …continued * indicates Special Function Registers (SFRs) that are bit addressable. Name Description Bit address IEN0* Interrupt Enable 0 Bit address IEN1* Interrupt Enable 1 Bit address IP0* Interrupt Priority 0 IP0H Interrupt Priority 0 ...
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Table 4. Special function registers …continued * indicates Special Function Registers (SFRs) that are bit addressable. Name Description SADEN Serial Port Address Enable Bit address SPCR SPI Control Register SPSR SPI Configuration Register SPDAT SPI Data SP Stack Pointer 2 ...
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... CODE Code memory space, accessed as part of program execution and via the MOVC instruction. The P89V660/662/664 have 16/32/ on-chip Code memory. 6.2.1 Expanded data RAM addressing The P89V660/662/664 have 512 B/1 kB RAM. See To access the expanded RAM, the EXTRAM bit must be set and MOVX instructions must be used. The extra memory is physically located on the chip and logically occupies the fi ...
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... ADDR < 0700H ADDR (89V664) (89V664) RD/WR asserted RD/WR asserted RD/WR not RD/WR asserted asserted Rev. 02 — 29 January 2008 P89V660/662/664 the oscillator frequency. In case ALE is 2 MOVX @Ri MOVX A, @Ri 0100H ADDR = any 0300H 0700H RD/WR asserted RD/WR not asserted © NXP B.V. 2008. All rights reserved. ...
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... FFH EXPANDED RAM 768 B 80H 7FH (INDIRECT ADDRESSING) 00H 000H FFFFH 0300H EXPANDED RAM Rev. 02 — 29 January 2008 P89V660/662/664 FFH (DIRECT (INDIRECT ADDRESSING) ADDRESSING) SPECIAL FUNCTION UPPER 128 B REGISTERS (SFRs) 80H INTERNAL RAM LOWER 128 B INTERNAL RAM (INDIRECT AND DIRECT ...
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... Reserved for future use. Should be set to ‘0’ by user programs. DPS Data pointer select. Chooses one of two Data Pointers for use by the program. See text for details. through an 8.2 k resistor as shown in SS Rev. 02 — 29 January 2008 P89V660/662/664 DPTR1 DPTR0 DPL 82H external data memory 002aaa518 ...
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... Flash memory 6.3.1 Flash organization The P89V660/662/664 program memory consists of a 16/32/64 kB block for user code. The flash can be read or written in bytes and can be erased in 128 pages. A chip erase function will erase the entire user code memory and its associated security bits. There are three methods of erasing or programming the fl ...
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... Power-on reset code execution The P89V660/662/664 contains two special flash elements: the Boot Vector and the Boot Status bit. Following reset, the P89V660/662/664 examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’ ...
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... NXP Semiconductors based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the P89V660/662/664 to establish the baud rate. The ISP firmware provides auto-echo of received characters. Once baud rate initialization has been performed, the ISP firmware will only accept Intel Hex-type records. Intel Hex ...
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... Erases code memory and security bits, programs default Boot vector and Status bit Subfunction code = 08 (Erase page, 128 high byte of page address (A[15:8 low byte of page address (A[7:0]) Example: :0300000308E000F2 (erase page at E000H) Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI © NXP B.V. 2008. All rights reserved ...
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... HH = high byte of timer low byte of timer checksum Example: :02000006FFFFcc (load T2 = FFFF) Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI © NXP B.V. 2008. All rights reserved ...
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... ACC = byte to program Return parameter(s): ACC = 00 = pass ACC = !00 = fail Input parameters 03H or 83H (WDT feed) DPH = memory address MSB DPL = memory address LSB Return parameter(s): ACC = device data Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI Table 12. © NXP B.V. 2008. All rights reserved ...
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... ACC = 00 SoftICE S/N-match DBL_CLK Input parameters 08H or 88H (WDT feed) DPH = page address high byte DPL = page address low byte Return parameter(s): ACC = 00 = pass ACC = !00 = fail Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI © NXP B.V. 2008. All rights reserved ...
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... STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I released. The P89V660/662/664 device provides two byte-oriented I simplicity, the description in this text is written for the primary interface. However, unless otherwise noted, the description applies to the secondary I consideration given to the SFR’ ...
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... I C-bus slave address register (S1ADR - address DBH) bit description Description no effect. General call bit. When set, the general call address (00H) is recognized, otherwise it is ignored. Table 17. Rev. 02 — 29 January 2008 P89V660/662/664 C-bus is in master mode C-bus device. Timer 1 should be ...
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... C-bus enters master mode, checks the bus and generates a START condition if Bit frequency at f osc 12-clock mode 6 MHz 12 MHz 6.25 12.5 Rev. 02 — 29 January 2008 P89V660/662/664 STO C-bus states is entered. When EA 2 C-bus. When the bus 2 C-bus interface. When clear, the I f ...
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... Reserved, are always set C-bus control register (S1CON - address D8H CR2 ENS1 STA bit rate 1 0 Table 17). ENS1 must be set enable the I Rev. 02 — 29 January 2008 P89V660/662/664 f divided by osc (Timer 1 reload) 2 C-bus interface. The least SC.1 SC.0 ...
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... C-bus Data Register (S1DAT). The SI bit must be cleared S slave address R logic 0 = write logic 1 = read from master to slave from slave to master 2 C-bus may switch to the Master Transmitter mode. Rev. 02 — 29 January 2008 P89V660/662/664 A DATA A DATA A/A P data transferred (n Bytes + acknowledge acknowledge (SDA LOW not acknowledge (SDA HIGH) ...
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... Table 25 for the status codes and actions. S slave address W logic 0 = write logic 1 = read from master to slave from slave to master Rev. 02 — 29 January 2008 P89V660/662/664 RS SLA W A DATA acknowledge (SDA LOW not acknowledge (SDA HIGH START condition P = STOP condition SLA = slave address ...
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... DATA logic 0 = write logic 1 = read A = acknowledge (SDA LOW not acknowledge (SDA HIGH) from master to slave S = START condition from slave to master P = STOP condition Rev. 02 — 29 January 2008 P89V660/662/664 2 A DATA A P data transferred (n Bytes + acknowledge) 002aaa933 © NXP B.V. 2008. All rights reserved. ...
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... STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1[6] I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram Rev. 02 — 29 January 2008 P89V660/662/664 8 I2ADR ADDRESS REGISTER COMPARATOR SHIFT REGISTER ACK I2DAT 8 BIT COUNTER/ ARBITRATION CCLK TIMING AND SYNC LOGIC AND CONTROL ...
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... Load data byte S1DAT action S1DAT action S1DAT action 1 1 Rev. 02 — 29 January 2008 P89V660/662/664 Next action taken by I hardware SLA+W will be transmitted; ACK bit will be received above; SLA+W will be 2 transmitted; I C-bus switches to Master Receiver mode ...
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... No S1DAT action S1DAT action S1DAT action Rev. 02 — 29 January 2008 P89V660/662/664 Next action taken by I hardware Data byte will be transmitted; ACK bit will be received Repeated START will be transmitted STOP condition will be transmitted ...
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... S1DAT action x 0 Read data byte read data byte x 0 Rev. 02 — 29 January 2008 P89V660/662/664 Next action taken by I hardware STA 0 0 Data byte will be received; NOT ACK bit will be returned Data byte will be received; ACK bit will be returned. ...
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... Rev. 02 — 29 January 2008 P89V660/662/664 Next action taken by I hardware Switched to not addressed SLA mode; no recognition of own SLA or general address Switched to not addressed SLA mode; Own SLA will be recognized; ...
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... Load data byte load data byte x 0 Load data byte load data byte x 0 Rev. 02 — 29 January 2008 P89V660/662/664 Next action taken by I hardware Switched to not addressed SLA mode; no recognition of own SLA or General call address Switched to not addressed SLA mode ...
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... S1DAT action S1DAT action 1 0 Table the oscillator frequency. 6 Rev. 02 — 29 January 2008 P89V660/662/664 Next action taken by I hardware Switched to not addressed SLA mode; no recognition of own SLA or General call address Switched to not addressed SLA mode; Own slave address will be recognized ...
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... T0M0 TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating mode M0 Operating mode Rev. 02 — 29 January 2008 P89V660/662/664 T1M0 T0GATE T0C/T 8048 timer ‘TLx’ serves as 5-bit prescaler. 16-bit Timer/Counter ‘THx’ and ‘TLx' are cascaded; there is no prescaler. ...
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... IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/LOW-state that triggers external interrupt 0. Rev. 02 — 29 January 2008 P89V660/662/664 8-bit auto-reload Timer/Counter ‘THx’ holds a value which reloaded into ‘TLx’ each time it overflows. (Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits ...
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... B/1 kB/2 kB RAM, dual TRn Figure 15 Figure 16. Overflow from TLn not only sets TFn, but also reloads TLn with the Rev. 02 — 29 January 2008 P89V660/662/664 overflow TLn THn TFn (5-bits) (8-bits) control (Figure 5). The GATE bit is in the TMOD Figure 14) ...
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... Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode 3, the P89V660/662/664 can look like it has an additional Timer. Note: When Timer Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator any application not requiring an interrupt ...
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... EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. T2MOD - Timer 2 mode control register (address C9H) bit allocation Rev. 02 — 29 January 2008 P89V660/662/664 T2OE Mode 0 16-bit auto reload 0 16-bit capture 1 Programmable Clock-Out 0 ...
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... Down Count Enable bit. When set, this allows Timer configured as an up/down-counter. Figure C/ TL2 (8-bits) control C/ TR2 capture RCAP2L RCAP2H control EXEN2 Rev. 02 — 29 January 2008 P89V660/662/664 18. TH2 TF2 (8-bits) EXF2 / 6 pulses. Since once osc © NXP B.V. 2008. All rights reserved. 2 C-bus, SPI timer 2 interrupt 002aaa523 ...
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... Timer 2 counting up automatically (DCEN = 0). C/ TL2 (8-bits) control C/ TR2 reload RCAP2L RCAP2H control EXEN2 RCAP2H RCAP2L (C/ frequency of signal on T2 pin osc Rev. 02 — 29 January 2008 P89V660/662/664 TH2 TF2 (8-bits) interrupt EXF2 002aaa524 © NXP B.V. 2008. All rights reserved. 2 C-bus, SPI timer 2 ( ...
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... DCEN = 1 and Timer 2 is enabled to count up or down. This mode allows pin (down-counting reload value) FFH TL2 (8-bits) control TR2 RCAP2L RCAP2H (up-counting reload value) RCAP2H RCAP2L Rev. 02 — 29 January 2008 P89V660/662/664 toggle FFH underflow TH2 TF2 (8-bits) overflow count direction down ...
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... B/1 kB/2 kB RAM, dual I shows Timer 2 in baud rate generator mode TR2 transition detector T2EX pin control EXEN2 – Rev. 02 — 29 January 2008 P89V660/662/664 Section 6.7 for details). When TCLK = 0, TL2 TH2 (8-bits) (8-bits) control reload RCAP2L RCAP2H timer 2 EXF2 interrupt ...
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... Timer 2 generated commonly used baud rates Oscillator frequency 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 12 MHz 6 MHz 6 MHz Rev. 02 — 29 January 2008 P89V660/662/664 Table 36 shows commonly used baud baud rate) Timer 2 RCAP2H RCAP2L ...
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... In Mode 0, SM2 should be ‘0’. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. Rev. 02 — 29 January 2008 P89V660/662/664 1 of the CPU clock frequency the CPU clock frequency, as determined ...
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... SM2 for exceptions). Must be cleared by software. SCON - Serial port control register (address 98H) SM0/SM1 mode definition UART mode 0: shift register 1: 8-bit UART 2: 9-bit UART 3: 9-bit UART Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI …continued Baud rate CPU clock / 6 variable CPU clock / 32 or CPU clock / 16 variable © ...
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... This device uses the methods presented in address has been received or not. P89V660_662_664_2 Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual I Figure 22 Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI to determine if a Given or Broadcast © NXP B.V. 2008. All rights reserved ...
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... UART to detect 'given address' in received data saddr(7) saden(7) rx_byte( saddr(0) saden(0) rx_byte(0) logic used by UART to detect 'given address' in received data multiprocessor communications is enabled Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI given_address_match broadcast_address_match 002aaa527 © NXP B.V. 2008. All rights reserved. (4) ( ...
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... Write collision flag protection (WCOL) • Wake-up from Idle mode (slave mode only) 6.8.2 SPI description The serial peripheral interface allows high-speed synchronous data transfer between the P89V660/662/664 and peripheral devices or between several P89V660/662/664 devices. Figure 23 P89V660_662_664_2 Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual I shows the correspondence between master and slave SPI devices. The SCK Rev. 02 — ...
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... Data transmission order MSB first LSB first in data transmission. MSTR Master/slave select master mode slave mode. CPOL Clock polarity SCK is high when idle (active LOW SCK is low when idle (active HIGH). Rev. 02 — 29 January 2008 P89V660/662/664 Figure 24 MSB slave LSB 8-BIT SHIFT REGISTER 002aaa528 ...
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... This bit is cleared by software. - Reserved for future use. Should be set to ‘0’ by user programs. SCK cycle # 1 2 (for reference) MOSI MSB 6 (from master) MISO MSB 6 (from slave) SS (to slave) Rev. 02 — 29 January 2008 P89V660/662/664 …continued 42. 42. divided by osc 12-clock mode 128 ...
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... Table 46). P89V660_662_664_2 Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual I SCK cycle # 1 2 (for reference) MOSI MSB 6 (from master) MISO MSB 6 (from slave) SS (to slave) Rev. 02 — 29 January 2008 P89V660/662/664 LSB the oscillator frequency, ...
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... B/1 kB/2 kB RAM, dual I 16 bits PCA TIMER/COUNTER Module functions: - 16-bit capture - 16-bit timer - 16-bit high speed output - 8-bit PWM - watchdog timer (module 4 only) Figure 27. Rev. 02 — 29 January 2008 P89V660/662/664 2 16 bits P1[3]/CEX0 MODULE0 MODULE1 P1[4]/CEX1 P1[5]/CEX2 MODULE2 P3[4]/T0/CEX3 MODULE3 MODULE4 ...
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... P89V660_662_664_2 Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual CCAPMn.0 ECCFn CMOD - PCA counter mode register (address C1H) bit allocation CIDL WDTE - Rev. 02 — 29 January 2008 P89V660/662/664 CCF4 CCF3 CCF2 CCF1 CCF0 IEN0.6 IEN0 CPS1 © NXP B.V. 2008. All rights reserved. ...
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... Must be cleared by software. CCF1 PCA Module 1 Interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 Interrupt Flag. Set by hardware when a match or capture occurs. Must be cleared by software. Rev. 02 — 29 January 2008 P89V660/662/664 Table 47 below osc / 6 osc 4 ...
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... Rev. 02 — 29 January 2008 P89V660/662/664 CAPNn MATn TOGn ECCFn Module function 0 no operation x 16-bit capture by a positive-edge trigger on CEXn x 16-bit capture by a negative-edge trigger on CEXn x 16-bit capture by any transition on CEXn x 16-bit software timer ...
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... Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual I - CCF4 CCF3 CCF2 (to CCFn) capture CAPPn CAPNn MATn TOGn 0 0 Rev. 02 — 29 January 2008 P89V660/662/664 CCON CCF1 CCF0 (C0h) PCA interrupt PCA timer/counter CH CL CCAPnH CCAPnL CCAPMn PWMn ECCFn (C2h to C6h) ...
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... COMPARATOR CH CL PCA timer/counter - ECOMn CAPPn CAPNn 0 0 (Figure 30) the CEX output (on port 1) associated with the PCA module will Rev. 02 — 29 January 2008 P89V660/662/664 CCF3 CCF2 CCF1 CCF0 (to CCFn) MATn TOGn PWMn ECCFn © NXP B.V. 2008. All rights reserved. ...
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... CH CL PCA timer/counter - ECOMn CAPPn CAPNn 0 0 CCAPnH CCAPnL 8-BIT COMPARATOR CL PCA timer/counter CAPNn MATn TOGn Rev. 02 — 29 January 2008 P89V660/662/664 CCF3 CCF2 CCF1 CCF0 (to CCFn) MATn TOGn PWMn ECCFn (Figure 31). Output frequency 0 CL CCAPnL CL CCAPnL 1 CCAPMn ...
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... B/1 kB/2 kB RAM, dual I EA ;Hold off interrupts CCAP4L,#00 ;Next compare value is within 255 counts of current PCA timer value CCAP4H,CH EA ;Re-enable interrupts Rev. 02 — 29 January 2008 P89V660/662/664 2 Figure 31 shows a diagram of how the 16 count of the PCA © NXP B.V. 2008. All rights reserved. C-bus, SPI ...
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... Vector address Interrupt enable 0003H EX0 000BH ET0 0013H EX1 001BH ET1 0023H ES0 002BH ES1 0033H EC 003BH ET2 0043H ES2 004BH ES3 Rev. 02 — 29 January 2008 P89V660/662/664 Table 53. Figure 32). Interrupt Service priority priority PX0/H 1 (highest) PT0/H 3 PX1/H 4 PT1/H 5 PS0/H 6 PS1/H 2 PPCH 8 ...
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... Fig 32. Interrupt structure P89V660_662_664_2 Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual I IP/IPH/IPA/IPAH IE and IEA registers IE0 IE1 global individual disable enables Rev. 02 — 29 January 2008 P89V660/662/664 registers 2 C-bus, SPI highest priority interrupt interrupt polling sequence lowest priority interrupt 002aab919 © NXP B.V. 2008. All rights reserved. ...
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... PS0 Serial Port Interrupt Priority Low Bit. PT1 Timer 1 Interrupt Priority Low Bit. PX1 External Interrupt 1 Priority Low Bit. PT0 Timer 0 Interrupt Priority Low Bit. PX0 External Interrupt 0 Priority Low Bit. Rev. 02 — 29 January 2008 P89V660/662/664 ES0 ET1 EX1 ...
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... IP1H - Interrupt priority 1 high register (address 92H) bit description Symbol Description - Reserved for future use. Should be set to ‘0’ by user programs. PS3H SPI Interrupt Priority High Bit. 2 PS2H I C-bus Interrupt Priority High Bit (secondary). Rev. 02 — 29 January 2008 P89V660/662/664 PS0H PT1H PX1H ...
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... ALE and PSEN signals at a LOW-state during power-down. External Interrupts are only active for level sensitive interrupts, if enabled. Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI Exited by Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits Idle mode, after the ISR RETI instruction, program ...
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... Table 68 shows the typical values for C Recommended values for C and n.c. external oscillator signal Rev. 02 — 29 January 2008 P89V660/662/664 and V specifications and C should be adjusted appropriately for 1 2 and C vs. resonator type for 1 2 ...
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... 4.5 V, SCL, SDA 3 4.5 V, ports 4.5 V, Port External Bus mode, ALE, PSEN 0.4 V, ports Rev. 02 — 29 January 2008 P89V660/662/664 2 Min Max 55 +125 65 +150 0 1.5 Min Typ Max [1] 10000 - - [1] 100 ...
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... must be externally limited as follows: OL may exceed the related specification. Pins are not guaranteed to sink current greater than the OH on ALE and PSEN to momentarily fall below the V OH Rev. 02 — 29 January 2008 P89V660/662/664 2 Min Typ Max [ 650 - - 10 ...
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... Typical active I DD (4) Typical idle I DD Fig 35. I vs. frequency DD P89V660_662_664_2 Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual Rev. 02 — 29 January 2008 P89V660/662/664 2 002aaa813 (1) (2) (3) ( internal clock frequency (MHz) © NXP B.V. 2008. All rights reserved. C-bus, SPI ...
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... IAP 0.25 2T cy(clk) T cy(clk) T cy(clk cy(clk) 3T cy(clk cy(clk cy(clk) 6T cy(clk cy(clk) 4T cy(clk) T cy(clk) 7T cy(clk cy(clk) Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI Typ Max Unit - 40 MHz - 20 MHz - 40 MHz cy(clk cy(clk) ...
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... Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual I t LHLL t LLIV t LLPL t PLIV t PLAZ t LLAX INSTR IN t AVIV A8 to A15 Rev. 02 — 29 January 2008 P89V660/662/664 t PLPH t PXAV t PXIZ t PXIX A15 002aaa548 2 C-bus, SPI © NXP B.V. 2008. All rights reserved ...
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... P2 A15 from DPH t t WLWH LLWL t LLAX t QVWH DATA OUT t AVWL P2[7: A15 from DPH Rev. 02 — 29 January 2008 P89V660/662/664 t WHLH t RHDZ from PCL A0 to A15 from PCH t WHLH t WHQX from PCL INSTR A15 from PCH 002aaa550 © ...
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... CHCL CLCX Oscillator 40 MHz Min Max 0.3 - 117 - 117 Rev. 02 — 29 January 2008 P89V660/662/664 Variable Min Max 0.35T 0.65T cy(clk) cy(clk) 0.35T 0.65T cy(clk) cy(clk CHCX t CLCH T cy(clk) 002aaa907 Variable Min Max 12T - cy(clk) 10T ...
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... XHDX valid valid valid valid Conditions before repeated START before STOP condition will be filtered out. Max capacitance on SDA and SCL = 400 pF. cy(clk) Rev. 02 — 29 January 2008 P89V660/662/664 set TI valid valid valid valid Input Output [1] 14T > 4.0 cy(clk) [1] 16T > 4.7 ...
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... Figure 44, 45 see Figure 44, 45 see Figure 42, 43, 44, 45 see Figure 42, 43, 44, 45 see Figure 42, 43, 44, 45 see Figure 42, 43, 44, 45 Rev. 02 — 29 January 2008 P89V660/662/664 t SU;STA STOP condition t BUF t SU;STO 0. suDAT2 t suDAT1 Variable clock f osc Min Max Min ...
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... SPIF SPIR t SPICLKL t SPICLKH t t SPIDSU SPIDH MSB/LSB SPIDV SPIOH master MSB/LSB out Rev. 02 — 29 January 2008 P89V660/662/664 SPIR LSB/MSB SPIDV SPIR master LSB/MSB out 002aaa908 LSB/MSB SPIDV SPIDV t SPIR master LSB/MSB out 002aaa909 © NXP B.V. 2008. All rights reserved. ...
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... SPIF SPIR t SPICLKL t SPICLKH t SPIR t SPICLKL t SPICLKH t SPIOH t SPIDV slave MSB/LSB out t t SPIDSU SPIDH MSB/LSB in Rev. 02 — 29 January 2008 P89V660/662/664 t SPIR t SPILAG t SPIOH slave LSB/MSB out not defined t t SPIDSU SPIDH LSB/MSB in 002aaa910 t SPIR t SPILAG t SPIOH t t SPIDV slave LSB/MSB out ...
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... B/1 kB/2 kB RAM, dual I to DUT V DD (n.c.) clock signal All other pins disconnected test condition, active mode DD (n.c.) clock signal All other pins disconnected test condition, Idle mode DD Rev. 02 — 29 January 2008 P89V660/662/664 to tester C L 002aaa555 RST EA ...
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... NXP Semiconductors Fig 49. I P89V660_662_664_2 Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual RST (n.c.) XTAL2 XTAL1 V SS All other pins disconnected test condition, Power-down mode DD Rev. 02 — 29 January 2008 P89V660/662/664 = DUT 002aaa558 2 C-bus, SPI © ...
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... 2.5 scale (1) ( 0.45 0.18 10.1 10.1 12.15 12.15 0.8 0.30 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC JEITA MS-026 Rev. 02 — 29 January 2008 P89V660/662/664 detail 0.75 1.2 1 0.2 0.2 0.1 0.45 0.8 EUROPEAN PROJECTION 2 C-bus, SPI SOT376 (1) ( ...
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... 0.81 16.66 16.66 16.00 16.00 17.65 1.27 0.66 16.51 16.51 14.99 14.99 17.40 0.032 0.656 0.656 0.63 0.63 0.695 0.05 0.026 0.650 0.650 0.59 0.59 0.685 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 02 — 29 January 2008 P89V660/662/664 detail 17.65 1.22 1.44 0.18 0.18 0.1 17.40 1.07 1.02 0.695 0.048 0.057 0.007 0.007 0.004 ...
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... Address Latch Enabled Central Processing Unit Erasable Programmable Read-Only Memory Electro-Magnetic Interference Pulse Width Modulator Random Access Memory Resistance-Capacitance Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI © NXP B.V. 2008. All rights reserved ...
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... Product data sheet 80C51 with 512 B/1 kB/2 kB RAM, dual I Data sheet status Change notice Product data sheet - description”: Type numbers modified. Product data sheet - Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI Supersedes P89V660_662_664_1 - © NXP B.V. 2008. All rights reserved ...
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... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 02 — 29 January 2008 P89V660/662/664 2 C-bus, SPI © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: P89V660_662_664_2 2 C-bus, SPI All rights reserved. Date of release: 29 January 2008 ...