p89v660 NXP Semiconductors, p89v660 Datasheet - Page 15

• Manufacturer Part Number: p89v660
• Description: P89v660/p89v662/p89v664 8-bit 80c51 5 V Low Power 16 Kb/32 Kb/64 Kb Flash Microcontroller With 512 B/1 Kb/2 Kb Ram, Dual I2c-bus, Spi
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89V660_662_664_2
Product data sheet
for the 89V662, above 6FFH for the 89V664) will access external off-chip memory and will
perform in the same way as the standard 8051, with P0 and P2 as data/address bus, and
P3[6] and P3[7] as write and read timing signals.
Table 6.
When EXTRAM = 0, MOVX @Ri and MOVX @DPTR will be similar to the standard 8051.
Using MOVX @Ri provides an 8-bit address with multiplexed data on Port 0. Other output
port pins can be used to output higher order address bits. This provides external paging
capabilities. Using MOVX @DPTR generates a 16-bit address. This allows external
addressing up the 64 kB. Port 2 provides the high-order eight address bits (DPH), and
Port 0 multiplexes the low order eight address bits (DPL) with data. Both MOVX @Ri and
MOVX @DPTR generates the necessary read and write signals (P3[6] - WR and P3[7] -
RD) for external memory use.
with EXTRAM bit.
The stack pointer (SP) can be located anywhere within the 256 B of internal RAM (lower
128 B and upper 128 B). The stack pointer may not be located in any part of the expanded
RAM.
Table 7.
Bit
7 to 2
1
0
AUXR
EXTRAM = 0
EXTRAM = 1
AUXR - Auxiliary register (address 8EH) bit description
External data memory RD, WR with EXTRAM bit
Symbol
-
EXTRAM
AO
MOVX @DPTR, A or MOVX A,
@DPTR
ADDR < 0100H
(89V660)
ADDR < 0300H
(89V662)
ADDR < 0700H
(89V664)
RD/WR asserted
RD/WR not
asserted
Rev. 02 — 29 January 2008
Description
Reserved for future use. Should be set to ‘0’ by user programs.
Internal/External RAM access using MOVX @Ri/@DPTR. When ‘1’,
accesses internal XRAM with address specified in MOVX instruction.
If address supplied with this instruction exceeds on-chip available
XRAM, off-chip RAM is accessed. When ‘0’, every MOVX instructions
targets external data memory by default.
ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a
constant rate of
active only during a MOVX or MOVC.
Table 7
80C51 with 512 B/1 kB/2 kB RAM, dual I
ADDR
(89V660)
ADDR
(89V662)
ADDR
(89V664)
RD/WR asserted
RD/WR asserted
shows external data memory RD, WR operation
1
2
the oscillator frequency. In case of AO = 1, ALE is
0100H
0300H
0700H
P89V660/662/664
MOVX @Ri, A or MOVX A, @Ri
ADDR = any
RD/WR asserted
RD/WR not asserted
© NXP B.V. 2008. All rights reserved.
2
C-bus, SPI
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