p89v660 NXP Semiconductors, p89v660 Datasheet - Page 39

• Manufacturer Part Number: p89v660
• Description: P89v660/p89v662/p89v664 8-bit 80c51 5 V Low Power 16 Kb/32 Kb/64 Kb Flash Microcontroller With 512 B/1 Kb/2 Kb Ram, Dual I2c-bus, Spi
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89V660_662_664_2
Product data sheet
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once every machine cycle.
When the samples show a high in one cycle and a low in the next cycle, the count is
incremented. The new count value appears in the register in the machine cycle following
the one in which the transition was detected. Since it takes two machine cycles (12
oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is
the oscillator frequency. There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once before it changes, it should
be held for at least one full machine cycle. In addition to the ‘Timer’ or ‘Counter’ selection,
Timer 0 and Timer 1 have four operating modes from which to select.
The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the Special Function
Register TMOD. These two Timer/Counters have four operating modes, which are
selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both
Timers/Counters. Mode 3 is different. The four operating modes are described in the
following text.
Table 26.
Not bit addressable; Reset value: 0000 0000B; Reset source(s): any source
Table 27.
Table 28.
Bit
7
6
5
4
3
2
1
0
M1
0
0
Bit
Symbol
TMOD - Timer/Counter mode control register (address 89H) bit allocation
TMOD - Timer/Counter mode control register (address 89H) bit description
TMOD - Timer/Counter mode control register (address 89H) M1/M0 operating
mode
T1GATE
Symbol
T1GATE
T1C/T
T1M1
T1M0
T0GATE
T0C/T
T0M1
T0M0
M0
0
1
7
Rev. 02 — 29 January 2008
T1C/T
6
Description
Gating control for Timer 1. When set, Timer/Counter is enabled only
while the INT1 pin is high and the TR1 control pin is set. When
cleared, Timer 1 is enabled when the TR1 control bit is set.
Timer or Counter select for Timer 1. Cleared for Timer operation (input
from CCLK). Set for Counter operation (input from T1 input pin).
Mode select for Timer 1.
Gating control for Timer 0. When set, Timer/Counter is enabled only
while the INT0 pin is high and the TR0 control pin is set. When
cleared, Timer 0 is enabled when the TR0 control bit is set.
Timer or Counter select for Timer 0. Cleared for Timer operation (input
from CCLK). Set for Counter operation (input from T0 input pin).
Mode Select for Timer 0.
Operating mode
0
1
T1M1
5
80C51 with 512 B/1 kB/2 kB RAM, dual I
T1M0
8048 timer ‘TLx’ serves as 5-bit prescaler.
16-bit Timer/Counter ‘THx’ and ‘TLx' are cascaded;
there is no prescaler.
4
T0GATE
P89V660/662/664
3
T0C/T
2
© NXP B.V. 2008. All rights reserved.
T0M1
1
2
C-bus, SPI
T0M0
39 of 89
1
0
12
of