p89v660 NXP Semiconductors, p89v660 Datasheet - Page 43

• Manufacturer Part Number: p89v660
• Description: P89v660/p89v662/p89v664 8-bit 80c51 5 V Low Power 16 Kb/32 Kb/64 Kb Flash Microcontroller With 512 B/1 Kb/2 Kb Ram, Dual I2c-bus, Spi
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89V660_662_664_2
Product data sheet
Table 31.
Table 32.
Bit addressable; Reset value: 00H
Table 33.
Table 34.
Not bit addressable; Reset value: XX00 0000B
RCLK+TCLK
0
0
0
1
X
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
Bit
Symbol
Timer 2 operating mode
T2CON - Timer/Counter 2 control register (address C8H) bit allocation
T2CON - Timer/Counter 2 control register (address C8H) bit description
T2MOD - Timer 2 mode control register (address C9H) bit allocation
Symbol
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2
CP/RL2
TF2
7
7
-
CP/RL2
0
1
0
X
X
Rev. 02 — 29 January 2008
EXF2
6
6
-
Description
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by
software. TF2 will not be set when either RCLK or TCLK = 1 or when
Timer 2 is in Clock-out mode.
Timer 2 external flag is set when Timer 2 is in capture, reload or baud
rate mode, EXEN2 = 1 and a negative transition on T2EX occurs. If
Timer 2 interrupt is enabled EXF2 = 1 causes the CPU to vector to the
Timer 2 interrupt routine. EXF2 must be cleared by software.
Receive clock flag. When set, causes the UART to use Timer 2
overflow pulses for its receive clock in modes 1 and 3. RCLK = 0
causes Timer 1 overflow to be used for the receive clock.
Transmit clock flag. When set, causes the UART to use Timer 2
overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0
causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable flag. When set, allows a capture or reload to
occur as a result of a negative transition on T2EX if Timer 2 is not
being used to clock the serial port. EXEN2 = 0 causes Timer 2 to
ignore events at T2EX.
Start/stop control for Timer 2. A logic ‘1’ enables the timer to run.
Timer or counter select. (Timer 2)
Capture/Reload flag. When set, captures will occur on negative
transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will
occur either with Timer 2 overflows or negative transitions at T2EX
when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is
ignored and the timer is forced to auto-reload on Timer 2 overflow.
0 = internal timer (f
1 = external event counter (falling edge triggered; external clock’s
maximum rate = f
TR2
1
1
1
1
0
RCLK
5
5
-
80C51 with 512 B/1 kB/2 kB RAM, dual I
TCLK
osc
4
4
-
osc
T2OE
0
0
1
0
X
/ 12.
/ 6)
EXEN2
P89V660/662/664
3
3
-
Mode
16-bit auto reload
16-bit capture
Programmable Clock-Out
Baud rate generator
off
TR2
2
2
-
© NXP B.V. 2008. All rights reserved.
T2OE
C/T2
1
1
2
C-bus, SPI
CP/RL2
DCEN
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0
0