p89v660 NXP Semiconductors, p89v660 Datasheet - Page 17

• Manufacturer Part Number: p89v660
• Description: P89v660/p89v662/p89v664 8-bit 80c51 5 V Low Power 16 Kb/32 Kb/64 Kb Flash Microcontroller With 512 B/1 Kb/2 Kb Ram, Dual I2c-bus, Spi
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89V660_662_664_2
Product data sheet
6.2.3 Reset
Table 8.
Not bit addressable; Reset value 00H
Table 9.
At initial power-up, the port pins will be in a random state until the oscillator has started
and the internal reset algorithm has weakly pulled all pins high. Powering up the device
without a valid reset could cause the MCU to start executing instructions from an
indeterminate location. Such undefined states may inadvertently corrupt the code in the
flash. A system reset will not affect the on-chip RAM while the device is running, however,
the contents of the on-chip RAM during power-up are indeterminate.
When power is applied to the device, the RST pin must be held high long enough for the
oscillator to start-up (usually several milliseconds for a low frequency crystal), in addition
to two machine cycles for a valid power-on reset. An example of a method to extend the
RST signal is to implement a RC circuit by connecting the RST pin to V
capacitor and to V
During initial power the POF flag in the PCON register is set to indicate an initial power-up
condition. The POF flag will remain active until cleared by software.
Following a reset condition, under normal conditions, the MCU will start executing code
from address 0000H in the user’s code memory. However if either the PSEN pin was low
when reset was exited, or the Status Bit was set = 1, the MCU will start executing code
from the boot address. The boot address is formed using the value of the boot vector as
the high byte of the address and 00H as the low byte.
Bit
7 to 4
3
2
1
0
Bit
Symbol
Fig 5. Dual data pointer organization
AUXR1 - Auxiliary register 1 (address A2H) bit allocation
-
AUXR1 - Auxiliary register 1 (address A2H) bit description
Symbol
-
GF2
0
-
DPS
7
DPS = 0
DPS = 1
SS
AUXR1 / bit0
-
through an 8.2 k resistor as shown in
DPS
Rev. 02 — 29 January 2008
6
DPTR0
DPTR1
Description
Reserved for future use. Should be set to ‘0’ by user programs.
General purpose user-defined flag.
This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by
incrementing AUXR1, without interfering with other bits in the register.
Reserved for future use. Should be set to ‘0’ by user programs.
Data pointer select. Chooses one of two Data Pointers for use by the
program. See text for details.
-
5
DPH
83H
80C51 with 512 B/1 kB/2 kB RAM, dual I
-
4
DPL
82H
DPTR1
DPTR0
GF2
P89V660/662/664
3
external data memory
Figure
0
2
002aaa518
6.
-
© NXP B.V. 2008. All rights reserved.
DD
1
through a 10 F
2
C-bus, SPI
DPS
17 of 89
0