p89v660 NXP Semiconductors, p89v660 Datasheet - Page 49

• Manufacturer Part Number: p89v660
• Description: P89v660/p89v662/p89v664 8-bit 80c51 5 V Low Power 16 Kb/32 Kb/64 Kb Flash Microcontroller With 512 B/1 Kb/2 Kb Ram, Dual I2c-bus, Spi
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89V660_662_664_2
Product data sheet
6.7.1 Mode 0
6.7.2 Mode 1
6.7.3 Mode 2
6.7.4 Mode 3
Serial data enters and exits through RXD and TXD outputs the shift clock. Only 8 bits are
transmitted or received, LSB first. The baud rate is fixed at
UART configured to operate in this mode outputs serial clock on TXD line no matter
whether it sends or receives data on RXD line.
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB first), and a stop bit (logical 1). When data is received, the stop bit is stored
in RB8 in Special Function Register SCON. The baud rate is variable and is determined
by the Timer
11 bits are transmitted (through TXD) or received (through RXD): start bit (logical 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). When data is
transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or (e.g. the
parity bit (P, in the PSW) could be moved into TB8). When data is received, the 9th data
bit goes into RB8 in Special Function Register SCON, while the stop bit is ignored. The
baud rate is programmable to either
by the SMOD1 bit in PCON.
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logical 0), 8
data bits (LSB first), a programmable 9th data bit, and a stop bit (logical 1). In fact, Mode 3
is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is
variable and is determined by the Timer
Table 37.
Bit addressable; Reset value: 00H
Table 38.
Bit
7
6
5
4
Bit
Symbol
SM0/FE
SCON - Serial port control register (address 98H) bit allocation
SCON - Serial port control register (address 98H) bit description
Symbol
SM0/FE
SM1
SM2
REN
1
2
7
overflow rate.
SM1
Rev. 02 — 29 January 2008
6
Description
The usage of this bit is determined by SMOD0 in the PCON register. If
SMOD0 = 0, this bit is SM0, which with SM1, defines the serial port
mode. If SMOD0 = 1, this bit is FE (Framing Error). FE is set by the
receiver when an invalid stop bit is detected. Once set, this bit cannot
be cleared by valid frames but can only be cleared by software. (Note:
It is recommended to set up UART mode bits SM0 and SM1 before
setting SMOD0 to ‘1’.)
With SM0, defines the serial port mode (see
Enables the multiprocessor communication feature in Modes 2 and 3.
In Mode 2 or 3, if SM2 is set to ‘1’, then Rl will not be activated if the
received 9th data bit (RB8) is ‘0’. In Mode 1, if SM2 = 1 then RI will not
be activated if a valid stop bit was not received. In Mode 0, SM2
should be ‘0’.
Enables serial reception. Set by software to enable reception. Clear by
software to disable reception.
SM2
5
80C51 with 512 B/1 kB/2 kB RAM, dual I
1
16
or
1
REN
2
1
overflow rate.
32
4
of the CPU clock frequency, as determined
TB8
P89V660/662/664
3
1
6
RB8
of the CPU clock frequency.
2
Table 39
© NXP B.V. 2008. All rights reserved.
TI
below).
1
2
C-bus, SPI
RI
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0