hsp50214 Intersil Corporation, hsp50214 Datasheet - Page 13

• Manufacturer Part Number: hsp50214
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

Each serial word has a programmable word width of either 8,
16, 24, or 32 bits (See Control Word 0, bits 4 and 5, for the
Carrier NCO programming and Control Word 11, bits 3 and
4, for Timing NCO programming). On the rising edge of the
clock, data on COF or SOF is clocked into an input shift reg-
ister. The beginning of a serial word is designated by assert-
ing either COFSYNC or SOFSYNC “high” one CLK period
prior to the first data bit.
The assertion of the COFSYNC (or SOFSYNC) starts a count
down from the programmed word width. On following CLKs,
data is shifted into the register until the specified number of
bits have been input. At this point the contents of the register
are transferred from the shift register to the respective 32-bit
holding register. The shift register can accept new data on the
following CLK. If the serial input word is defined to be less
than 32 bits, it will be transferred to the MSBs of the 32-bit
holding register and the LSBs of the holding register will be
zeroed. See Figure 14 for details.
NOTE: Serial Data must be loaded MSB first, and COFSYNC or
NOTE: COF loading and timing is relative to CLKIN while SOF
NOTE: T
FIGURE 14. HOLDING REGISTERS LOAD SEQUENCE FOR
†
†
IGURE 13. SERIAL INPUT TIMING FOR COF AND SOF INPUTS
COFSYNC/
OTE: Data must be loaded MSB first.
SOFSYNC
32
24
16
Serial word width can be: 8, 16, 24, 32 bits wide.
T
8
30
28
26
22
20
18
14
12
10
D
†
†
†
†
6
4
2
0
CLKIN
is determined by the COFSYNC, COFSYNC rate.
COF/
SOF
SOFSYNC should not be asserted for more than one CLK
cycle.
loading and timing is relative to PROCCLK.
D
2
can be 0, and the fastest rate is with 8-bit word width.
6
COF AND SOF SERIAL OFFSET FREQUENCY
DATA
10
14
CLK TIMES
MSB
18
COFSYNC, SOFSYNC
(8)
TO HOLDING REGISTER
ASSERTION OF
22
(16)
DATA TRANSFERRED
26
(24)
30
(32)
34
LSB
T
T
T
T
38
D
D
D
D
††
††
††
††
MSB
42
46
50
HSP50214
54
13
CIC Decimation Filter
The mixer output may be filtered with the CIC filter or it may be
routed directly to the halfband filters. The CIC filter is used to
reduce the sample rate of a wideband signal to a rate that the
halfbands and programmable filters can process, given the
maximum computation speed of PROCCLK. (See Halfband
and FIR Filter Sections for techniques to calculate this value.)
Prior to the CIC filter, the output of the mixer goes through a
barrel shifter. The shifter is used to adjust the gain in 6dB
steps to compensate for the variation in filter gain with deci-
mation. (See Equation 6). Fine gain adjustments must be
done in the AGC section. The shifter is controlled by the sum
of a 4-bit CIC Shift Gain word from the microprocessor and a
3-bit gain word from the GAINADJ(2:0) pins. The three bit
value is pipelined to match the delay of the input samples.
The sum of the 3 and 4-bit shift gain words saturates at a
value of 15. Table 3 details the permissible values for the
GAINADJ(2:0) barrel shifter control, while the Figure 15
shows the permissible CIC Shift Gain values.
The CIC filter structure for the HSP50214 is fifth order; that
is it has five integrator/comb pairs. A fifth order CIC has
84dB of alias attenuation for output frequencies below 1/8
the CIC output sample rate.
The decimation rate of the CIC filter is programmed in Control
Word 0, bits 12 - 7. The CIC Shift Gain is programmed in Con-
trol Word 0, bits 16-13. The CIC Bypass is set in Control Word
0, bit 6.
TABLE 3. GAIN ADJUST CONTROL AND CIC DECIMATION
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GAIN VALUE
4
(dB)
8
12
18
24
30
36
42
0
6
12
FIGURE 15. CIC SHIFT GAIN VALUES
16
20
8-BIT INPUT
10-BIT INPUT
12-BIT INPUT
14-BIT INPUT
24
GAIN ADJ(2:0)
28
DECIMATION (R)
000
001
010
011
100
101
110
111
32
36
ALLOWABLE CIC SHIFT
GAINS ARE BELOW THE
CURVES
40
44
DECIMATION
48
MAX. CIC
52
32
27
24
21
18
16
12
10
56
60
64