hsp50214 Intersil Corporation, hsp50214 Datasheet - Page 32

• Manufacturer Part Number: hsp50214
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

Word 20 has been set to route data to AOUT(7:0) and
BOUT(7:0), then the microprocessor must place a value on
the PDC input pins SEL(2:0), to choose which data type will
be output on AOUT(7:0) and BOUT(7:0). Table 17 defines
the data types in terms of SEL(2:0). With the control lines
set, the selected data is read MSByte on AOUT(7:0) and
LSByte on BOUT(7:0) when OEAL and OEBL (are low).
New data only read when OEBL goes low, so use P for 8-
bit modes. Programming SEL(2:0) = 110 outputs a 16-bit
status signal on AOUT and BOUT. The FIFO status includes
FULL, EMPTY, FIFO Depth, and READYB. These status sig-
nals are defined in Table 18.
|r|
Q
DATA
FIGURE 34. 16-BIT MICROPROCESSOR INTERFACE
NEW
I
SEQUENCER
TABLE 17. BUFFER RAM OUTPUT SELECT DEFINITIONS
WRITE
16
16
16
16
16
SEL(2:0)
000
001
010
011
100
101
110
111
BUFFER RAM MODE BLOCK DIAGRAM
“SET OF WORDS”
INCR
WR
SEQUENCER
PROCCLK
ADDRESS
DUAL
PORT
RAM
I Data
Q Data
Magnitude
Phase
Frequency
Unused
Memory Status
Reading this address increments to the next
sample set
INCR
RD
OUTPUT DATA TYPE
I
Q
|r|
STATUS
0
1
2
3
4
6
OUTPUT
DATA
OEBL
SEL(2:0)
HSP50214
32
NOTE: In the Status output, BOUT(7:0) are all GND.
Figure 35 shows the interface between a 16-bit microproces-
sor (or other baseband processing engine) and the Buffer
RAM output section of the Programmable Down Converter,
configured for data output via the parallel outputs AOUT and
BOUT. In the 16-bit microprocessor interface configuration,
the Buffer RAM pointer is incremented when the Processor
reads address SEL(2:0) = 7 and OEBL = 0.
After reset, the FIFO must be incremented to read the first
sample set. This is because the RAM read and write pointers
cannot point to the same address. Thus, the FIFO pointer
must move to the next address before reading the next set of
data (I, Q, |r|, , and f) samples. 4 PROCCLK cycles are
required after an increment before reading can resume. The
FIFO write pointer is reset to zero (the first data sample) when
Control Word 22 is written to via the 8-bit microprocessor
interface. See the Microprocessor Read Section for more
detail on how to obtain the Buffer RAM output with this tech-
nique. Figure 36 shows the timing diagram required for paral-
lel output operations. In this diagram, only the I, Q and
Frequency data are taken from each sample before incre-
menting to the next sample. Figure 36 assumes that the
pointer has already been incremented into a sample.
NOTE: For the very first sample read, the pointer must be incre-
Figure 36 shows INTRRP going low before the FIFO is read.
The FIFO can be read before the number of samples
reaches the INTRRP pointer. The number of samples in the
FIFO must be monitored by the user via a status read.
LOCATION
AOUT BIT
(7:5)
mented first and 4 PROCCLKs must pass before this
sample can be read.
1-0
4
3
2
TABLE 18. STATUS BIT DEFINITIONS
FIFO depth - When in FIFO mode, these bits
are the current depth of the FIFO.
EMPTY - When in FIFO mode, the FIFO is
empty, and the read pointer cannot be ad-
vanced. Active High.
FULL - When in FIFO mode, the FIFO is full,
and new samples will not be written.
Active High.
READYB - When in FIFO mode, the output buff-
er has reached the programmed threshold. In
the snapshot mode, the programmed number
of samples have been taken. Active Low.
GND
INFORMATION