hsp50214 Intersil Corporation, hsp50214 Datasheet - Page 35

• Manufacturer Part Number: hsp50214
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

Snap Shot Operation
The snapshot mode takes sets of adjacent samples at pro-
grammed intervals. It is provided for tracking algorithms that
do not require processing of every sample, but do require
sets of adjacent samples. For example, bit sync algorithms
have narrow loop bandwidths that may not need to be
updated every sample. Computing the bit phase may require
4 adjacent samples at 2 times the baud rate. The snapshot
mode allows the processor to implement the tracking algo-
rithms for high speed data without having to handle every
data sample.
The interval from the start of one snapshot to the start of a
second snapshot is programmed into bits 11-4 (where bit 11
is the MSB) of Control Word 21. The actual interval is the
value programmed plus 1. If bits 11-4 = 11111111, then the
interval is set to 256. If sample sets are to be taken every 4
samples, then bits 11-4 = 00000011.
Figure 40 shows the relationship between the snapshot
samples and the snapshot interval.
The PDC begins to fill the buffer each time an interval num-
ber of samples have passed. The number of sample sets the
PDC writes into the buffer is programmed into bits 3-0 of
Control Word 21. The number of samples stored is the pro-
grammed value and may be from 1 to 8 sample sets. A sam-
ple set consists of I, Q, |r|,
In snap shot operations, the buffer is read the same as for
FIFO operations. Figures 34 and 36 describe the block and
timing diagrams required to output data on AOUT(7:0) and
BOUT(7:0). Table 17 summarizes the selectable output sig-
nals. The method for reading data through the microproces-
sor section in snap shot mode is identical to the method
described in the FIFO mode subsection and the Micropro-
cessor Read Section.
Avoiding Timing Pitfalls When Using the Buffer RAM
Output Port
In snapshot mode, the whole buffer is written whenever the
interval counter has timed-out. After time-out, old data can
be written over. Thus, the data contained within the buffer
must be retrieved before time-out to avoid data loss.
It may be desirable to disable the INTRRPT into the control-
ling microprocessor during read cycles to avoid the generat-
ing extra interrupts. Figure 41 details how the WRITE
address can trigger extra interrupts Care must be taken to
either read sufficient data out of memory or RESET the
addressing to ensure that a complete set of data is the
cause of the interrupt.
0
# SAMPLES = 4
1
FIGURE 40. SNAP SHOT SAMPLING
ADJACENT
2
SAMPLES
INTERVAL = 64
3
4
and .
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63
64
HSP50214
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35
Microprocessor Write Section
The
addressing scheme where a 32-bit data word is first loaded
in a four 8-bit byte master registers using four writes via
C(7:0). The desired destination register address is then writ-
ten to another address using C(7:0). Writing this address
triggers a circuit that generates a pulse, synchronous to
clock, that loads the destination register. The sync circuits
and data words are synchronized to different clocks, CLKIN
or PROCCLK, depending on the destination registers.
A(2:0) determines the destination for the data on bus,
C(7:0). Table 19 shows the address map for microproces-
sor interface. Figure 42 shows the control register loading
sequence. The data in C(7:0) and address map in A(2:0) is
loaded into the PDC on the rising edge of WR and is
latched into the master register on the rising edge of WR
and A(2:0) = 100. Four clocks must pass before loading the
next control word to guarantee that the data has been
transferred.
Some registers can be loaded (i.e., transferred from the
master register to a configuration register or from a holding
register to an active register) by initiating a sync. For exam-
ple, to load the AGC Gain, the value of the AGC gain is first
loaded into the holding registers, then a transfer is initiated
by SYNCIN2 if Control Word 8, bit 29 = 1. This allows the
AGC gain to be loaded by detecting a system event, such as
a start of a new burst. Bit 20 of Control Word 0 has the same
effect on the Carrier NCO center frequency for assertion of
SYNCIN1, except it transfers from a dedicated holding regis-
ter - not the master register.
A COMPLETE SET OF 3 DATA SAMPLES IS IN MEMORY AT INTRRP
B: FALSE TRIGGERED INTERRUPT READ/WRITE SEQUENCE
FIGURE 41. AVOIDING FALSE INTRRP ASSERTIONS
microprocessor
INTRRP
THE THIRD INTERRUPT HAS ONLY 1 NEW DATA ENTRY
INTRRP
WR
WR
A: NORMAL READ/WRITE SEQUENCE
(INSTEAD OF 3) AT INTRRP
RD
RD
INTRRP
write
INTRRP
WR
WR
section
INTRRP
INTRRP
uses
WR
RD
an
TIME
TIME
RD
indirect