hsp50214 Intersil Corporation, hsp50214 Datasheet - Page 34

• Manufacturer Part Number: hsp50214
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

FIFO Operation via 8-Bit Processor
Interface
The Buffer RAM Output may also be accessed via the 8-bit
microprocessor interface C(7:0). Figure 39 shows the con-
ceptual configuration of the 8-bit processor interface. Con-
trol Word 20 bit 24 must be set to 0 in order to obtain Buffer
RAM data to this output. The Microprocessor Read section
describes how to read the data from each sample out of the
C(7:0) interface.
CONTROL
WORD 23
A(2:0)
DATA
NEW
RD
|r|
Q
I
SEQUENCER
WRITE
16
16
16
16
16
ADDRESS “5”
0: I;Q
1: |r|;
2:
4: INPUT AGC
5: AGC; TIMING
(R/ SELECTED)
(I/Q SELECTED)
WRITE
FIGURE 39. 8-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM
WRITES TO
SNAPSHOT
PROCCLK
DATARDY
DATARDY
INTRPT
“SET OF WORDS”
INCR
WR
RAM
SEQUENCER
ADDRESS
DUAL
PORT
R2, R1, R0
A2, A1, A0
RAM
INCR
RD
I/Q
STATUS
INT(22:16)
I
Q
|r|
INT(15:0)
R/
DELAY TO DATARDY DEPENDS ON LENGTH OF FIR IF FREQ CHOSEN
I
TIMING
AGC
0
1
2
3
4
R1
FIGURE 38. RAM LOAD SEQUENCE
Q
R0
0
1
2
3
A1
0
R0 A1
1
R
A0
HSP50214
R2
MSByte
LSByte
34
0
1
Recall that INTRRP stays low for 8 PROCCLK cycles. The
FIFO can be read before the INTRRP signal goes low; the
number of samples in the FIFO must be monitored by the user.
Figure 38 illustrates the timing for RAM load sequence.
The read pointer of the FIFO is incremented when Control
Word 23 is written to. The data can not be read from the
next sample until 4 PROCCLKs after the Buffer RAM
pointer has been incremented. Control Word 22 is used to
reset the Read and Write pointers of the Buffer RAM output
to the first sample to 000 and 007 for write and read
respectively.
A2
0
1
A1
A0
OUTPUT
DATA
R2 R1 R0 A2 A1 A0 SELECTION
X
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
X
0
0
0
0
1
1
1
1
0
0
1
0
0
0
1
1
1
1
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
1
1
1
X NOT USED
X NOT USED
0 RAM I LSB
1 RAM I MSB
0 RAM Q LSB
1 RAM Q MSB
0 RAM |r| LSB
1 RAM |r| MSB
0 RAM
1 RAM
0 RAM
1 RAM
0 INPUT INTEG LSB
1 INPUT INTEG NMSB
0 INPUT INTEG MSB
0 AGC LSB
1 AGC MSB
0 TIMING LSB
1 TIMING MSB
1 STATUS
LSB
MSB
LSB
MSB