hsp50214 Intersil Corporation, hsp50214 Datasheet - Page 24

• Manufacturer Part Number: hsp50214
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

of instructions per second) effective due to symmetry. If the
CDMA filter (loaded into the programmable FIR section)
requires an impulse response with a span of 12 chips, the fil-
ter at 2x the chip-rate would need 24 taps. The 24 taps would
translate into 59MIPS = (1.2288MHz)(2)(24). To get the same
filtering at 8x the chip rate would require 944MIPS =
(1.2288MHz)(8)(96). Direct 8x filtering can not be accom-
plished with the programmable filter alone because 944MIPS
are much greater that the 60MIPs effective limit set by PROC-
CLK. It is necessary to decimate down to 2x the chip rate to
get a realistic number of filter taps. Both interpolation halfband
filters are used to obtain an 8x CDMA output. The MIPS for
the first halfband equals (2.4576MHz)(Number of Multiplies
for first halfband), and the second equal (4.9152MHz)(Num-
ber of Multiplies for second halfband). Combined halfband fil-
ters is equal to (1.2228MHz)(4)(48) = 236MIPS. Thus the
MIPS are 18 and 25 for the first and second halfbands respec-
tively, and 42 for both.
Timing NCO
The Timing NCO is very similar to the carrier NCO phase
accumulator section. It provides the NCO driven sample pulse
and associated phase information to the re-sampling filter pro-
cess described in the Resampler Filter section. The Timing
NCO does not include the SIN/COS section found in the Car-
rier NCO. The top level block diagram is shown in Figure 26.
The programmable parameters for the Timing NCO include
an Enable External Timing NCO Sync (Control Word 11, bit
5), the serial word width, Number of Offset Frequency Bits
(Control Word 11 bits 3-4), an Enable Offset Frequency con-
trol (Control Word 11, bit 2), a Clear NCO Accumulator con-
EN EXT TIMING NCO SYNC
†
NUMBER OF SOF BITS
TIMING PHASE STROBE
SYNCIN2
PHASE OFFSET
Controlled via microprocessor interface.
ENABLE SOF
TIMING NCO
SOFSYNC
FIGURE 26. TIMING NCO BLOCK DIAGRAM
SOF
†
†
ACCUMULATOR
SOF
SYNC
SHIFT REG
†
PHASE
32
†
SYNC
MUX
REG
†
0
TIMING NCO CENTER
FREQUENCY
8
32
REG
REG
5
REG
+
+
SCF
†
MUX
SYNC
CARRY OUT = RUN
FILTER STROBE
FILTER PHASE
SELECT
0
TIMING FREQ
STROBE
TIMING NCO
UPDATE
LOAD ON
PH ACC
CLEAR
PHASE
ACC
HSP50214
†
†
†
24
trol (Control Word 11, bit 1), a Timing NCO Phase
Accumulator Load On Update control (Control Word 11, bit
0), the Timing NCO Center Frequency (Control Word 12), a
Timing Phase Offset (Control Word 13, bits 0-7), a Timing
Frequency Strobe (Control Word 14) and a Timing Phase
Strobe (Control Word 15). Refer to the Carrier Synthesizer
Mixer section for a detailed discussion of the serial interface
for the Timing NCO offset frequency word.
A timing error detector is provided for measuring the phase
difference between the timing NCO and a external clock input,
REFCLK. Timing Error is generated by comparing the values
of two programmable counters. One counter is clocked with
the Timing NCO carry out and the other is clocked by the
REFCLK. The 12-bit NCO Divide parameter is set in Control
Word 18, bits 16-27. The NCO Divide parameter is the pre-
load to the counter that is clocked by the Timing NCO carry
out. The 12-bit Reference Divide parameter is set in Control
Word 18, bits 0-11, and is the preload for the counter that is
clocked by the Reference clock. Figure 27 details the block
diagram of the timing error generation circuit. The 16 bits of
timing error are available both as a PDC serial output and as a
processor read parameter. See the Processor Read Section
for more details on accessing this value.
†
Figure 27A illustrates an application where the Timing Error
Generator is used to lock the receiver samples with a trans-
mit data rate. In this example, the receive samples are at
four times the transmit data rate. An external loop filter is
required, whose frequency error output is fed into the Timing
NCO. This allows the loop to track out the long term drift
between the receive sample rate and the transmit data clock.
REFCLK
Controlled via microprocessor interface.
TIMING
NCO
ACC
FIGURE 27. TIMING ERROR GENERATION
PROGRAMMABLE
PROGRAMMABLE
NCO DIVIDE
DIVIDER
REFERENCE
DIVIDER
DIVIDE
†
†
(NCO DIVIDE)/2
12
4
EN
+
-
†
TE(15:0)