hsp50214 Intersil Corporation, hsp50214 Datasheet - Page 4

• Manufacturer Part Number: hsp50214
• Description: Programmable Downconverter
• Manufacturer: Intersil Corporation

Pin Descriptions
SYNCOUT
SEROUTA
SEROUTB
SERSYNC
DATARDY
MSYNCO
SYNCIN1
SYNCIN2
SERCLK
SEL(2:0)
REFCLK
MSYNCI
INTRRP
SEROE
NAME
OEAH
OEBH
OEAL
OEBL
C(7:0)
A(2:0)
WR
RD
TYPE
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
(Continued)
Output Strobe Signal. Active low. Indicates when new data from the Direct Output Port section is avail-
able. DATARDY is asserted for one PROCCLK cycle during the first clock cycle that data is available
on the parallel out busses. See Output Section.
Output enable for the MSByte of the AOUT bus. Active Low.
Output enable for the LSByte of the AOUT bus. Active Low.
Output enable for the MSByte of the BOUT bus. Active Low.
Output enable for the LSByte of the BOUT bus. Active Low.
Select Address is used to choose which information in a data set from the Buffer RAM Output Port is
sent to the least significant bytes of AOUT and BOUT. SEL2 is the MSB.
Interrupt Output. Active low. This output is asserted for 8 PROCCLK cycles when the Buffer RAM Out-
put Port is ready for reading.
Serial Output Bus A Data. I, Q, magnitude, phase, frequency, timing error and AGC information can
be sequenced in programmable order. See Output Section and Microprocessor Write Section.
Serial Output Bus B Data. Contents may be related to SEROUTA. I, Q, magnitude, phase, frequency,
timing error and AGC information can be sequenced in programmable order. See Output Section and
Microprocessor Write Section.
Output Clock for Serial Data Out. Derived from PROCCLK as given by control word 20 in the Micro-
processor Write Section.
Serial Output Sync Signal. Serves as serial data strobes. See Output Section and Microprocessor
Write Section.
Serial Output Enable. When high, the SEROUTA, SEROUTB, SERCLK, and SERSYNC signals are
set to a high impedance.
Processor Interface Data Bus. See Microprocessor Write Section. C7 is the MSB.
Processor Interface Address Bus. See Microprocessor Write Section. A2 is the MSB.
Processor Interface Write Strobe. C(7:0) is written to control words selected by A(2:0) in the Program-
mable Down Converter on the rising edge of this signal. See Microprocessor Write Section.
Processor Interface Read Strobe. C(7:0) is read from output or status locations selected by A(2:0)
in the Programmable Down Converter on the falling edge of this signal. See Microprocessor Read
Section.
Reference Clock. Used as an input clock for the timing error detector. The timing error is computed
relative to REFCLK. REFCLK frequency must be less than or equal to PROCCLK/2.
Multiple Chip Sync Output. Provided for synchronizing multiple parts when CLKIN and PROCCLK are
asynchronous. MSYNCO is the synchronization signal between the input section operating under
CLKIN and the back end processing operating under PROCCLK. This output sync signal from one
part is connected to the MSYNCI signal of all the HSP50214s.
Multiple Chip Sync Input. The MSYNCI pin of all the parts should be tied to the MSYNCO of one part.
NOTE: MSYNCI must be connected to an MSYNCO signal for operation.
CIC Decimation/Carrier NCO Update Sync. Can be used to synchronize the CIC section, carrier NCO
update, or both. See the Multiple Chip Synchronization Section and Control Word 0 in the Micropro-
cessor Write Section. Active High.
FIR/Timing NCO Update/AGC Gain Update Sync. Can be used to synchronize the FIR, Timing NCO
update, AGC gain update, or any combination of the above. See the Multiple Chip Synchronization
Section and Control Words 7, 8, and 10 in the Microprocessor Write Section. Active High.
Strobe Output. This synchronization signal is generated by the P interface for synchronizing multiple
parts. Can be generated by PROCLK or CLKIN (see Control word 0 and Control word 24 in the Mi-
croprocessor Write Section). Active High.
HSP50214
4
DESCRIPTION