s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 112

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

D a t a
S h e e t
Data
D0
D1
Rising edge of next clock cycle
AVD#
following last wait state triggers
next burst data
total number of clock cycles
following AVD# falling edge
OE#
1
2
3
4
5
6
7
CLK
0
1
2
3
4
5
number of clock cycles
programmed
Wait State Decoding Addresses:
A14, A13, A12 = “111” ⇒ Reserved
A14, A13, A12 = “110” ⇒ Reserved
A14, A13, A12 = “101” ⇒ 5 programmed, 7 total
A14, A13, A12 = “100” ⇒ 4 programmed, 6 total
A14, A13, A12 = “011” ⇒ 3 programmed, 5 total
A14, A13, A12 = “010” ⇒ 2 programmed, 4 total
A14, A13, A12 = “001” ⇒ 1 programmed, 3 total
A14, A13, A12 = “000” ⇒ 0 programmed, 2 total
Note: Figure assumes address D0 is not at an address boundary, active clock edge is rising, and wait state is set to “101”.
Figure 22.25 Example of Wait States Insertion
110
S29WS128J/064J
S29WS-J_M0_A4 June 24, 2005