s71ws256jc0 Meet Spansion Inc., s71ws256jc0 Datasheet - Page 134

• Manufacturer Part Number: s71ws256jc0
• Description: Stacked Multi-chip Product Mcp 128/64 Megabit 8m/4m X 16-bit Cmos 1.8 Volt-only, Simultaneous Read/write, Burst Mode Flash Memory With Cellularram
• Manufacturer: Meet Spansion Inc.

Note: Valid/invalid data delayed for one clock after Wait transitions (BCR[8] = 1). See
March 9, 2005 CellRam_03_A0
29.3.3
29.3.4
29.3.5
Note: Data valid/invalid immediately after Wait transitions (BCR[8] = 0). See
Output Impedance (BCR[5]): Default = Outputs Use Full Drive
Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for
different data bus loading scenarios. The reduced-strength options are intended for stacked chip
(Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-drive-
strength option minimizes the noise generated on the data bus during Read operations. Normal
output drive strength should be selected when using a discrete CellularRAM device in a more
heavily loaded data bus environment. Outputs are configured at full drive strength during testing.
Wait Configuration (BCR[8]): Default = Wait Transitions One
Clock Before Data Valid/Invalid
The Wait configuration bit is used to determine when Wait transitions between the asserted and
the de-asserted state with respect to valid data presented on the data bus. The memory controller
will use the Wait signal to coordinate data transfer during synchronous Read and Write operations.
When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after Wait transitions
to the de-asserted or asserted state, respectively
the Wait signal transitions one clock period prior to the data bus going valid or invalid
(Figure
Wait Polarity (BCR[10]): Default = Wait Active High
The Wait polarity bit indicates whether an asserted Wait output should be High or Low. This bit
will determine whether the Wait signal requires a pull-up or pull-down resistor to maintain the de-
asserted state.
29.6).
A d v a n c e
DQ[15:0]
DQ[15:0]
WAIT
WAIT
CLK
CLK
Figure 29.5 Wait Configuration (BCR[8] = 0)
Figure 29.6 Wait Configuration (BCR[8] = 1)
High-Z
Data immediately valid (or invalid)
I n f o r m a t i o n
Data valid (or invalid) after one clock delay
High-Z
CellularRAM Type 2
Data[0]
(Figure 29.5
Data[1]
Data[0]
and
Figure
Figure
Figure
29.7.
29.7). When A8 = 1,
29.7.
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